专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20140070281A1 HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：高电压场效应晶体管及其制造方法
公开(公告)号：US20140070281A1
公开(公告)日：2014-03-13
申请号：US13608260
申请日：2012-09-10
申请人： Li-Fan Chen , Wing-Chor Chan , Jeng Gong
发明人： Li-Fan Chen , Wing-Chor Chan , Jeng Gong
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0634 , H01L29/0692 , H01L29/1066
摘要： A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
摘要翻译：提供了高压结场效应晶体管及其制造方法。高压结场效应晶体管包括基极，漏极，源极和P型顶层。漏极和源极设置在基底之上。在源极和漏极之间形成沟道。 P型顶层设置在通道上方。

22. 发明授权

US08652895B2 Semiconductor memory device and a method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08652895B2
公开(公告)日：2014-02-18
申请号：US13176196
申请日：2011-07-05
申请人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
发明人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/337 , H01L21/8244
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的层压体，形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜和栅电极形成为覆盖层压体的侧壁。垂直MISFET是完全耗尽型MISFET。

23. 发明授权

US08633083B1 Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant 有权
标题翻译：具有源极穿通保护植入物的金属氧化物半导体场效应晶体管的装置和方法
公开(公告)号：US08633083B1
公开(公告)日：2014-01-21
申请号：US13964958
申请日：2013-08-12
申请人： Spansion LLC
发明人： Imran Khan , Richard Fastow , Dong-Hyuk Ju
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66575 , H01L29/66659 , H01L29/7835
摘要： A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.
摘要翻译：具有源极穿通保护植入物的金属氧化物半导体场效应晶体管（MOSFET）。具体地，MOSFET包括半导体衬底，形成在半导体衬底上的栅极堆叠，源极和漏极区域以及保护注入。半导体衬底包括第一p型掺杂浓度。源极和漏极区域包括n型掺杂浓度，并且形成在半导体衬底中的栅极堆叠的相对侧上。保护注入包括第二p型掺杂浓度，并且形成在源极区域下方的半导体衬底中并且围绕源极区域以保护源极区域与对应于漏极区域的耗尽区域保护。

24. 发明授权

US08618583B2 Junction gate field effect transistor structure having n-channel 有权
标题翻译：具有n沟道的结栅场效应晶体管结构
公开(公告)号：US08618583B2
公开(公告)日：2013-12-31
申请号：US13108305
申请日：2011-05-16
申请人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/66 , H01L21/70 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
摘要翻译：本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

25. 发明授权

US08519452B2 Semiconductor device with junction field-effect transistor and manufacturing method of the same 有权
标题翻译：具有结型场效应晶体管的半导体器件及其制造方法
公开(公告)号：US08519452B2
公开(公告)日：2013-08-27
申请号：US13248173
申请日：2011-09-29
申请人： Rajesh Kumar Malhan
发明人： Rajesh Kumar Malhan
IPC分类号： H01L29/812 , H01L21/337 , H01L29/768
CPC分类号： H01L29/8083 , H01L29/0661 , H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/872
摘要： A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.
摘要翻译：公开了一种具有JFET的半导体器件。半导体器件包括形成在沟槽中的沟槽和接触嵌入层。栅极线连接到触点嵌入层，使得栅极线经由接触嵌入层连接到嵌入式栅极层。在这种结构中，可以减小嵌入式栅极层与栅极线之间的接触结构。

26. 发明授权

US08481372B2 JFET device structures and methods for fabricating the same 有权
标题翻译： JFET器件结构及其制造方法
公开(公告)号：US08481372B2
公开(公告)日：2013-07-09
申请号：US12333012
申请日：2008-12-11
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L21/337
CPC分类号： H01L27/098 , H01L21/22 , H01L21/225 , H01L21/2251 , H01L21/3226 , H01L21/385 , H01L27/108 , H01L27/1203 , H01L29/66893 , H01L29/66901 , H01L29/80 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
摘要翻译：根据本技术，提供了一种JFET器件结构及其制造方法。具体地，提供了包括具有源极和漏极的半导体衬底的晶体管。晶体管还包括形成在源极和漏极之间的半导体衬底中的掺杂沟道，该沟道被配置为在源极和漏极之间传导电流。此外，晶体管具有包括在沟道上形成的半导体材料的栅极和栅极每侧上的电介质间隔物。源极和漏极在空间上与栅极分离，使得栅极不在漏极和源极之上。

27. 发明授权

US08450164B2 Methods of forming a plurality of capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US08450164B2
公开(公告)日：2013-05-28
申请号：US12710077
申请日：2010-02-22
申请人： Vishwanath Bhat , Kevin R. Shea , Farrell Good
发明人： Vishwanath Bhat , Kevin R. Shea , Farrell Good
IPC分类号： H01L21/337
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/91
摘要： A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
摘要翻译：形成多个电容器的方法包括在电容器阵列区域和电路区域上接收的绝缘材料。阵列区域包括在单独的电容器存储节点位置处接收的绝缘材料内的多个电容器电极开口。中间区域包括沟槽。导电材料形成在开口内并抵靠沟槽的侧壁部分，以小于完全填充沟槽。覆盖材料形成在沟槽内的导电材料的正面外侧界面和电路区域的绝缘材料之间。用液体蚀刻溶液蚀刻阵列区域内的绝缘材料，该液体蚀刻溶液有效地暴露阵列区域内的导电材料的外侧壁部分并露出沟槽内的导电材料。阵列区域内的导电材料被并入多个电容器中。

28. 发明授权

US08404531B2 Method for fabricating a power transistor 有权
标题翻译：功率晶体管的制造方法
公开(公告)号：US08404531B2
公开(公告)日：2013-03-26
申请号：US13349038
申请日：2012-01-12
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Yi-Chun Shih , Main-Gwo Chen
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Yi-Chun Shih , Main-Gwo Chen
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L21/2253 , H01L21/2255 , H01L29/0634 , H01L29/1095
摘要： A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.
摘要翻译：一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电型载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

29. 发明授权

US08343824B2 Gallium nitride material processing and related device structures 有权
标题翻译：氮化镓材料加工及相关器件结构
公开(公告)号：US08343824B2
公开(公告)日：2013-01-01
申请号：US12143727
申请日：2008-06-20
申请人： Edwin Lanier Piner , Jerry Wayne Johnson , John Claassen Roberts
发明人： Edwin Lanier Piner , Jerry Wayne Johnson , John Claassen Roberts
IPC分类号： H01L21/337 , H01L21/00 , H01L29/12 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/02381 , H01L21/02458 , H01L21/0251 , H01L21/0254 , H01L21/02658 , H01L21/02664 , H01L29/2003 , H01L29/66462 , H01L33/007 , H01L33/0079 , H01S5/32341
摘要： Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.
摘要翻译：描述了氮化镓材料器件和相关工艺。在一些实施例中，通过去除下面的区域来暴露氮化镓材料区域的N面。

30. 发明申请

US20120309142A1 TRANSISTORS FOR REPLACING METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS IN NANOELECTRONICS 审中-公开
标题翻译：用于替代纳米电子学中的金属氧化物半导体场效应晶体管的晶体管
公开(公告)号：US20120309142A1
公开(公告)日：2012-12-06
申请号：US13560329
申请日：2012-07-27
申请人： Mark S. Miller , Justin B. Jackson , Divesh Kapoor , Justin Millis
发明人： Mark S. Miller , Justin B. Jackson , Divesh Kapoor , Justin Millis
IPC分类号： G06F17/50 , H01L21/337
CPC分类号： H01L21/8232 , H01L27/098
摘要： Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.
摘要翻译：结栅场效应晶体管（JFET）被证明是栅极长度小于约40nm的金属氧化物半导体场效应晶体管（MOSFET）的可行替代品，为缩小MOSFET的栅极泄漏问题提供了替代方案。集成电路设计可以具有替代现有的基于MOSFET的逻辑单元的互补JFET（CJFET）逻辑单元，以产生经修订的集成电路设计。集成电路可以包括JFET，其中沟道包括宽带隙半导体材料，并且栅极包括窄带隙半导体材料。 JFET和MOSFET晶体管的混合可以包含在集成电路设计中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式