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1. 发明授权

US09600384B2 System-on-chip verification 有权
公开(公告)号：US09600384B2
公开(公告)日：2017-03-21
申请号：US14513361
申请日：2014-10-14
申请人： Spansion LLC
发明人： Qamrul Hasan , William Chu , Lijun Pan , Hongjun Xue
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F11/22 , G06F11/261 , G06F17/5031 , G06F2217/84
摘要： Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals. During the hardware verification process, the AIC configures at least one of the communication protocols to enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a register-transfer level model is used for a least one of the plurality of peripherals. The AIC may further configure at least one of the communication protocols to enforce one or more constraints on the transactions to achieve increased hardware verification coverage.

2. 发明授权

US09502979B2 Output switching circuit 有权
标题翻译：输出开关电路
公开(公告)号：US09502979B2
公开(公告)日：2016-11-22
申请号：US14598647
申请日：2015-01-16
申请人： Spansion LLC
发明人： Takeshi Wakii , Akihito Yoshioka
IPC分类号： G01F1/40 , H02M3/158 , H03K17/687
CPC分类号： H02M3/158 , H02M3/1588 , H03K17/6872 , Y02B70/1466
摘要： An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.
摘要翻译：一种输出切换电路，包括：开关电路，具有连接到高电压电源的第一晶体管，与低电压电源连接的第二晶体管，以及连接在第一和第二晶体管之间的输出端子; 比较单元，其将输入信号与通过低通滤波器的输出端子的输出信号的反馈获得的反馈信号进行比较，以生成比较信号; 以及驱动脉冲发生单元，其根据比较信号产生用于驱动第一晶体管的第一驱动脉冲和用于驱动第二晶体管的第二驱动脉冲。

3. 发明申请

US20160277184A1 DEVICE AND METHOD FOR RESISTING NON-INVASIVE ATTACKS 有权
标题翻译：用于阻止非入侵攻击的装置和方法
公开(公告)号：US20160277184A1
公开(公告)日：2016-09-22
申请号：US14659924
申请日：2015-03-17
申请人： Spansion LLC
发明人： Toru Katayama
IPC分类号： H04L9/08
CPC分类号： H04L9/002 , G06F7/523 , H04L2209/08
摘要： A device and method for resisting, non-invasive attacks are disclosed herein. The device includes a random number generator that generates a random number, and a multiplier that multiplies first data and second data in a unit of a bit length determined based on the random number.
摘要翻译：本文公开了一种用于抵抗非侵入式攻击的装置和方法。该装置包括产生随机数的随机数发生器，以及以基于随机数确定的位长度为单位乘以第一数据和第二数据的乘法器。

4. 发明授权

US09362293B2 CT-NOR differential bitline sensing architecture 有权
标题翻译： CT-NOR差分位线检测架构
公开(公告)号：US09362293B2
公开(公告)日：2016-06-07
申请号：US14135863
申请日：2013-12-20
申请人： Spansion LLC
发明人： Hagop Nazarian , Richard Fastow , Lei Xue
IPC分类号： H01L27/115 , G11C16/10 , H01L21/66
CPC分类号： H01L27/115 , G11C7/18 , G11C16/10 , G11C16/24 , G11C2207/002 , H01L22/14
摘要： Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.
摘要翻译：在此描述提供实现高读取性能的非易失性半导体存储器架构。一方面，以串联方式布置的存储晶体管阵列被配置为控制传输晶体管的栅极电压。传输晶体管又使电流在半导体存储器架构的两个金属位线之间流动。因此，可以测量和利用两个金属位线的相对电压或相对电流来确定串联晶体管阵列的晶体管的编程或擦除状态。在特定方面，选择具有小电容的晶体管用于传输晶体管，导致传输晶体管栅极电压/电流相对于晶体管阵列电流的快速对应。这可以基于两个金属位线的差分感测来相当于晶体管阵列的快速读取时间。

5. 发明申请

US20160099721A1 Analog-Digital Conversion System and Method for Controlling the Same 有权
标题翻译：模拟数字转换系统及其控制方法
公开(公告)号：US20160099721A1
公开(公告)日：2016-04-07
申请号：US14503585
申请日：2014-10-01
申请人： Spansion LLC
发明人： Tetsuro OKURA , Yusaku Ito , Hirohiko Sadamatsu
IPC分类号： H03M1/06 , H03M1/44 , H03F1/08 , H03M1/12
CPC分类号： H03M1/0609 , H03F3/387 , H03F3/45475 , H03F3/45968 , H03F2200/372 , H03F2203/45551 , H03F2203/45634 , H03M1/0626 , H03M1/124
摘要： An analog-digital conversion system includes an analog-digital converter; and a preamplifier circuit which is provided in the previous stage of the analog-digital converter and differentially amplifies an input analog signal. In the preamplifier circuit, an offset voltage and/or a noise occurs and/or is mixed. The preamplifier circuit outputs two types of analog amplified differential signals where a phase is inverted only with respect to the offset voltage and/or the noise. The analog-digital converter has an averaging circuit which averages the two types of analog amplified differential signals for each clock cycle of sampling preceding an analog-digital conversion and outputs a digital signal based on the differential signal averaged by the averaging circuit.
摘要翻译：模拟数字转换系统包括模数转换器; 以及前置放大器电路，其被提供在模拟数字转换器的前一级并差分地放大输入的模拟信号。在前置放大器电路中，发生偏移电压和/或噪声和/或混合。前置放大器电路输出两种类型的模拟放大差分信号，其中仅相对于偏移电压和/或噪声反相。模拟数字转换器具有平均电路，其对模数转换之前的采样的每个时钟周期对两种类型的模拟放大差分信号进行平均，并且基于由平均电路平均的差分信号输出数字信号。

6. 发明授权

US09305614B2 Memory device with internal combination logic 有权
标题翻译：具有内部组合逻辑的存储器件
公开(公告)号：US09305614B2
公开(公告)日：2016-04-05
申请号：US13725415
申请日：2012-12-21
申请人： Spansion LLC
发明人： Mark Alan McClain
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C8/00 , G11C7/1006 , G11C7/1009 , G11C2207/104
摘要： Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.
摘要翻译：本发明的实施例包括用于将数据处理逻辑与存储器集成的装置，方法和系统。存储器集成电路的实施例被设计为对存储器集成电路内的存储器阵列中的数据执行任务。存储器集成电路可以包括存储器阵列，数据存取组件，数据保持组件和逻辑组件。数据访问组件可以耦合到存储器阵列并且被配置为向存储器阵列提供地址。数据保持组件可以耦合到存储器阵列并且被配置为临时将数据存储在位于地址处的存储器阵列中。逻辑组件可以耦合到数据访问组件和数据保持组件两者，并且被配置为使用从数据保持组件接收的数据来执行任务。逻辑组件可以包括组合或顺序逻辑。

7. 发明授权

US09209197B2 Memory gate landing pad made from dummy features 有权
标题翻译：由虚拟特征制成的记忆门着陆垫
公开(公告)号：US09209197B2
公开(公告)日：2015-12-08
申请号：US13715828
申请日：2012-12-14
申请人： Spansion LLC
发明人： Mark Ramsbey , Chun Chen , Unsoon Kim , Shenqing Fang
IPC分类号： H01L29/792 , H01L27/115 , H01L21/768 , H01L21/8234 , H01L29/423 , H01L29/66 , H01L29/788
CPC分类号： H01L27/11524 , H01L21/76877 , H01L21/76897 , H01L21/823475 , H01L27/11563 , H01L27/11568 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.
摘要翻译：本文描述的实施例通常涉及用于接触的层站门板及其制造方法。在两个特征之间形成桥以允许接触件至少部分地布置在桥上。着陆桥上的触点避免了额外的制造步骤来创建联系人的目标。

8. 发明授权

US09167647B1 Control circuit and control method for dimming a lighting device 有权
标题翻译：用于调光照明装置的控制电路和控制方法
公开(公告)号：US09167647B1
公开(公告)日：2015-10-20
申请号：US14315713
申请日：2014-06-26
申请人： Spansion LLC
发明人： Koji Takekawa , Kazuyoshi Arimura
IPC分类号： H05B37/02 , H05B33/08
CPC分类号： H05B33/0845 , H05B33/0815 , H05B33/0824
摘要： A control circuit comprises a power supply unit configured to generate a voltage to be supplied to a load by turning on and off a first switch in response to a drive signal and control a drive current of the load by turning on and off a second switch in response to a control signal, a first controller configured to perform a first PWM control of the drive signal, based on a measurement value of the drive current, a second controller configured to perform a second PWM control of the control signal, based on an external signal, and a synchronous controller configured to synchronize an on-period of one period of the control signal to he a multiple of one period of the drive signal. Further, in the control circuit, during the on-period of the control signal, an inductor current for generating the drive current is cut off for a portion of every period of the drive signal.
摘要翻译：控制电路包括：电源单元，被配置为通过响应于驱动信号接通和断开第一开关来产生要提供给负载的电压，并通过接通和断开第二开关来控制负载的驱动电流响应于控制信号，第一控制器被配置为基于驱动电流的测量值来执行驱动信号的第一PWM控制，第二控制器，被配置为基于外部的控制信号执行控制信号的第二PWM控制信号和同步控制器，其被配置为使控制信号的一个周期的接通周期与驱动信号的一个周期的倍数同步。此外，在控制电路中，在控制信号的导通期间，用于产生驱动电流的电感电流在驱动信号的每个周期的一部分被切断。

9. 发明授权

US09142270B2 Pipelining in a memory 有权
标题翻译：流淌在记忆中
公开(公告)号：US09142270B2
公开(公告)日：2015-09-22
申请号：US13790979
申请日：2013-03-08
申请人： Spansion LLC
发明人： Michael Achter , Evrim Binboga , Marufa Kaniz , Murni Mohd-Salleh
IPC分类号： G11C7/00 , G11C7/12 , G11C7/10 , G11C29/02
CPC分类号： G11C7/12 , G11C7/1039 , G11C29/023 , G11C29/028
摘要： A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
摘要翻译：一种包括存储单元阵列的系统，包括多个存储单元，以及写入装置，用于产生多个背靠背写入脉冲以从多个存储单元写入到目标存储器单元，多个背靠背写入脉冲在重叠持续时间期间重叠，所述重叠持续时间可基于存储器单元阵列的性能参数来调节。

10. 发明授权

US09142209B2 Data pattern analysis 有权
标题翻译：数据模式分析
公开(公告)号：US09142209B2
公开(公告)日：2015-09-22
申请号：US14258076
申请日：2014-04-22
申请人： Spansion LLC
发明人： Richard Fastow , Qamrul Hasan
IPC分类号： G10L15/06 , G06K9/00
CPC分类号： G10L15/063 , G06K9/00979 , G10L15/02 , G10L15/14 , G10L15/28 , G10L2015/025
摘要： A method and apparatus receive multiple data pattern analysis requests from a controller and substantially simultaneously perform, with multiple data pattern analysis units, multiple data pattern analyses on one or more portions of a data stream.
摘要翻译：一种方法和装置从控制器接收多个数据模式分析请求，并且与多个数据模式分析单元基本上同时执行在数据流的一个或多个部分上的多个数据模式分析。

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