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1. 发明授权

US08723235B2 JFET devices with increased barrier height and methods of making the same 有权
标题翻译：具有增加势垒高度的JFET器件及其制造方法
公开(公告)号：US08723235B2
公开(公告)日：2014-05-13
申请号：US13400442
申请日：2012-02-20
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L29/812
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/267 , H01L29/66848 , H01L29/66916 , H01L29/808 , H01L29/812 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
摘要翻译：提供了提供具有改进的操作特性的JFET晶体管的器件和方法。具体地，本发明的一个或多个实施例涉及具有较高二极管导通电压的JFET晶体管。例如，一个或多个实施例包括具有掺杂碳化硅栅极的JFET，而其他实施例包括具有金属栅极的JFET。一个或多个实施例还涉及其中可以使用改进的JFET的系统和装置，以及制造改进的JFET的方法。

2. 发明授权

US08481372B2 JFET device structures and methods for fabricating the same 有权
标题翻译： JFET器件结构及其制造方法
公开(公告)号：US08481372B2
公开(公告)日：2013-07-09
申请号：US12333012
申请日：2008-12-11
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L21/337
CPC分类号： H01L27/098 , H01L21/22 , H01L21/225 , H01L21/2251 , H01L21/3226 , H01L21/385 , H01L27/108 , H01L27/1203 , H01L29/66893 , H01L29/66901 , H01L29/80 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
摘要翻译：根据本技术，提供了一种JFET器件结构及其制造方法。具体地，提供了包括具有源极和漏极的半导体衬底的晶体管。晶体管还包括形成在源极和漏极之间的半导体衬底中的掺杂沟道，该沟道被配置为在源极和漏极之间传导电流。此外，晶体管具有包括在沟道上形成的半导体材料的栅极和栅极每侧上的电介质间隔物。源极和漏极在空间上与栅极分离，使得栅极不在漏极和源极之上。

3. 发明申请

US20130140631A1 SEMICONDUTOR ISOLATION STRUCTURE AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20130140631A1
公开(公告)日：2013-06-06
申请号：US13310145
申请日：2011-12-02
申请人： Kamal Karda , Chandra Mouli
发明人： Kamal Karda , Chandra Mouli
IPC分类号： H01L29/78 , H01L21/762 , B82Y99/00 , B82Y40/00
CPC分类号： H01L21/76224 , H01L21/76232 , H01L27/10823 , H01L27/10844 , H01L27/10885 , H01L27/10891 , H01L29/66666
摘要： A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

4. 发明授权

US08455919B2 High density thyristor random access memory device and method 有权
标题翻译：高密度可控硅随机存取存储器件及方法
公开(公告)号：US08455919B2
公开(公告)日：2013-06-04
申请号：US12838803
申请日：2010-07-19
申请人： Suraj J. Mathew , Chandra Mouli
发明人： Suraj J. Mathew , Chandra Mouli
IPC分类号： H01L21/332 , H01L29/66
CPC分类号： H01L29/74
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.
摘要翻译：显示存储器件和制造存储器件的方法。所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。提供的方法允许存储器阵列中的迹线布线形成在存储器件的表面上或附近。

5. 发明授权

US08404536B2 Method for fabricating stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors 有权
标题翻译：用碳化硅基非晶硅薄膜晶体管制造堆叠式非易失性存储器的方法
公开(公告)号：US08404536B2
公开(公告)日：2013-03-26
申请号：US13186822
申请日：2011-07-20
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L21/18 , H01L21/336
CPC分类号： H01L27/11551 , H01L21/02529 , H01L21/3148 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L29/1608 , H01L29/66068 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.
摘要翻译：堆叠的非易失性存储器件使用垂直堆叠的非晶硅基薄膜晶体管。晶体管或单元的每个层由具有预定浓度的碳的沉积的a-Si沟道区形成，以形成富含碳的硅膜或碳化硅膜，这取决于碳含量。电介质堆叠形成在沟道区域层上。在一个实施例中，电介质叠层是ONO结构。控制栅极形成在电介质叠层上。该结构垂直重复以形成堆叠结构。在一个实施方案中，对于每个随后形成的层，沟道区域层的碳含量降低。

6. 发明申请

US20130009208A1 HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD 有权
标题翻译：高密度THYRISTOR随机访问存储器件及方法
公开(公告)号：US20130009208A1
公开(公告)日：2013-01-10
申请号：US13621002
申请日：2012-09-15
申请人： Suraj J Mathew , Chandra Mouli
发明人： Suraj J Mathew , Chandra Mouli
IPC分类号： H01L29/74
CPC分类号： H01L29/74
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.
摘要翻译：显示存储器件和制造存储器件的方法。所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。提供的方法允许存储器阵列中的迹线布线形成在存储器件的表面上或附近。

7. 发明授权

US08304707B2 Method and apparatus providing an optical guide in image sensor devices 有权
标题翻译：在图像传感器装置中提供光导的方法和装置
公开(公告)号：US08304707B2
公开(公告)日：2012-11-06
申请号：US12393812
申请日：2009-02-26
申请人： Ji Soo Lee , Jeff A. Mckee , Chandra Mouli
发明人： Ji Soo Lee , Jeff A. Mckee , Chandra Mouli
IPC分类号： H01L27/00
CPC分类号： H01L27/14625 , H01L27/14609 , H01L27/14623 , H01L27/14627 , H01L27/14643
摘要： A device and method for providing an optical guide of a pixel to guide incoming light to/from a photo-conversion device of the pixel to improve the optical crosstalk immunity. The optical guide includes an optically reflecting barrier formed as a trench filled with a material which produces reflection. The trench fill material may have an index of refraction that is less than the index of refraction of the material used for the trench surrounding layers to provide a light reflective structure or the trench fill material may provide a reflection surface.
摘要翻译：一种用于提供像素的光导以将来自/来自像素的光转换装置的入射光引导以提高光学串扰抗扰度的装置和方法。光导包括形成为填充有产生反射的材料的沟槽的光反射势垒。沟槽填充材料可以具有小于用于沟槽周围层的材料的折射率以提供光反射结构或者沟槽填充材料可以提供反射表面的折射率。

8. 发明授权

US08298846B2 Transparent conductor based pinned photodiode 有权
标题翻译：透明导体固定光电二极管
公开(公告)号：US08298846B2
公开(公告)日：2012-10-30
申请号：US12704769
申请日：2010-02-12
申请人： Chandra Mouli , Howard E. Rhodes
发明人： Chandra Mouli , Howard E. Rhodes
IPC分类号： H01L21/00
CPC分类号： H01L27/14609 , H01L27/14601 , H01L27/1463 , H01L27/14689
摘要： A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A gate conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a layer of indium-tin oxide. The transparent conductor can be biased to reduce the need for a surface dopant in creating a pinned photodiode region. The biasing of the transparent conductor produces a hole-rich accumulation region near the surface of the substrate. The gate conductor material permits a greater amount of charges from short wavelength light to be captured in the photo-sensing region in the substrate, and thereby increases the quantum efficiency of the photosensor.
摘要翻译：具有改善的短波长光响应的钉扎光电二极管。在本发明的示例性实施例中，在半导体衬底中的掺杂的掩埋区域上形成栅极氧化物。栅极导体形成在栅极氧化物的顶部。栅极导体是透明的，在一个实施例中是一层氧化铟锡。透明导体可以被偏置以减少在产生钉扎光电二极管区域时对表面掺杂剂的需要。透明导体的偏压在基板的表面附近产生一个富含孔的堆积区域。栅极导体材料允许在衬底中的光敏区域中捕获较短波长的光的更大量的电荷，从而提高光电传感器的量子效率。

9. 发明申请

US20120064685A1 Methods of making random access memory devices, transistors, and memory cells 有权
标题翻译：制造随机存取存储器件，晶体管和存储器单元的方法
公开(公告)号：US20120064685A1
公开(公告)日：2012-03-15
申请号：US13301916
申请日：2011-11-22
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L21/336
CPC分类号： H01L29/66666 , H01L21/8213 , H01L27/105 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/41783 , H01L29/4236 , H01L29/7827 , H01L29/785 , Y10S438/931
摘要： A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
摘要翻译：存储器件包括存储器单元阵列和外围设备。至少一些单独的记忆单元包括含有SiC的碳酸化部分。至少一些外围设备不包括任何碳酸化部分。晶体管包括第一源极/漏极，第二源极/漏极，包括在第一和第二源极/漏极之间包含SiC的半导体衬底的碳酸化部分的沟道以及与沟道的相对侧可操作地相关联的栅极。

10. 发明申请

US20120056151A1 Memory Devices, Memory Device Constructions, Constructions, Memory Device Forming Methods, Current Conducting Devices, and Memory Cell Programming Methods 有权
标题翻译：存储器件，存储器件结构，构造，存储器件形成方法，电流传导器件和存储器单元编程方法
公开(公告)号：US20120056151A1
公开(公告)日：2012-03-08
申请号：US13292932
申请日：2011-11-09
申请人： Chandra Mouli
发明人： Chandra Mouli
IPC分类号： H01L29/15
CPC分类号： H01L27/2418 , G11C5/02 , G11C11/34 , G11C11/39 , G11C11/4026 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/003 , G11C2013/009 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2216/08 , H01L29/6609 , H01L45/00 , H01L45/141 , H01L45/145 , H01L45/16
摘要： Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
摘要翻译：一些实施例包括具有字线，位线，可选择性地以三种或更多种不同电阻状态中的一种状态配置的存储器元件的存储器件，以及被配置为允许电流从字线通过存储器元件流过到位线的二极管，电压施加在字线和位线之间，并且如果电压增加或减小则降低电流。一些实施例包括具有字线，位线，可选择性地以两种或多种不同电阻状态之一配置的存储器元件的存储器件，被配置为阻止第一电流响应于第一电压从位线流向字线的第一二极管，以及第二二极管，包括电介质材料，并被配置为响应于第二电压允许第二电流从字线流到位线。

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