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21. 发明申请

US20170287458A1 APPARATUS FOR TRACKING THE FUNDAMENTAL FREQUENCY OF A SIGNAL WITH HARMONIC COMPONENTS STRONGER THAN THE FUNDAMENTAL 有权
公开(公告)号：US20170287458A1
公开(公告)日：2017-10-05
申请号：US15626147
申请日：2017-06-18
申请人： Brian James Kaczynski , Noam Lavi
发明人： Brian James Kaczynski , Noam Lavi
IPC分类号： G10H5/00 , H03M7/16 , H03L7/16
CPC分类号： G10H5/002 , G06F1/022 , G10H2250/101 , G10H2250/161 , H03L7/091 , H03L7/0991 , H03L7/0992 , H03L7/16 , H03L7/181 , H03L7/197 , H03L2207/50 , H03M7/16
摘要： Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

22. 发明授权

US09748937B1 Superconducting digital phase rotator 有权
公开(公告)号：US09748937B1
公开(公告)日：2017-08-29
申请号：US15155687
申请日：2016-05-16
申请人： Hypres, Inc.
发明人： Amol Ashok Inamdar
IPC分类号： H04L7/00 , H03K5/131 , H03K3/38 , H03L7/16 , H03K5/00
CPC分类号： H03K5/131 , H03K3/38 , H03K5/13 , H03K2005/00286 , H03L7/0805 , H03L7/0814 , H03L7/16
摘要： An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

23. 发明授权

US09698800B2 System and method for clock generation with an output fractional frequency divider 有权
$System and method for clock generation with an output fractional frequency divider$
公开(公告)号：US09698800B2
公开(公告)日：2017-07-04
申请号：US14660711
申请日：2015-03-17
申请人： Linear Technology Corporation
发明人： Jan-Michael Stevenson
IPC分类号： H03L7/16 , H03K21/10 , H03K23/48
CPC分类号： H03L7/16 , H03K21/10 , H03K23/486
摘要： A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

24. 发明申请

US20170187364A1 DIGITAL DUTY CYCLE CORRECTION FOR FREQUENCY MULTIPLIER 有权
公开(公告)号：US20170187364A1
公开(公告)日：2017-06-29
申请号：US15153496
申请日：2016-05-12
申请人： QUALCOMM Incorporated
发明人： Dongmin Park , Jong Min Park , Lai Kan Leung
IPC分类号： H03K5/156 , H03L7/089 , H04L7/033 , H03L7/093 , H03L7/16 , H04L7/00 , H03L7/081 , H03L7/091
CPC分类号： H03K5/1565 , H03L7/0814 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/16 , H03L2207/50 , H04L7/0087 , H04L7/0331 , H04L7/0332
摘要： An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.

25. 发明申请

US20170163271A1 DIRECT DIGITAL SYNTHESIZING METHOD AND DIRECT DIGITAL SYNTHESIZER 有权
公开(公告)号：US20170163271A1
公开(公告)日：2017-06-08
申请号：US15325855
申请日：2015-06-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Huagang WU
IPC分类号： H03L7/16
CPC分类号： G06F1/0321 , G06F1/022 , H03L7/16
摘要： A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase lookup table according to the amplitude value (S103); if the second phase is less than the first phase, adjusting and outputting the amplitude value (S105); or else, outputting the original amplitude value (S106); and performing, by a digital-to-analog converter, a digital-to-analog conversion according to the output amplitude value to obtain a sinusoidal wave (S107); wherein, for a N-bit phase accumulation module and a D-bit digital-to-analog converter, the preset phase lookup table has 2D−1-1 phase boundary value records corresponding to 0˜2D−1-2 amplitudes, each phase boundary value is stored in N-2 bits. A direct digital frequency synthesizer applying the above method is also disclosed.

26. 发明授权

US09571107B2 High-order sigma delta for a divider-less digital phase-locked loop 有权
标题翻译：用于无分频数字锁相环的高阶西格玛delta
公开(公告)号：US09571107B2
公开(公告)日：2017-02-14
申请号：US14317435
申请日：2014-06-27
申请人： Intel IP Corporation
发明人： Rotem Banin , Elan Banin , Ofir Degani
IPC分类号： H03L7/08 , H03L7/085 , H04B1/40 , H03L7/16 , H03M7/30
CPC分类号： H03L7/085 , H03L7/16 , H03L2207/50 , H03M7/3004 , H04B1/40
摘要： Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
摘要翻译：这里描述的是与无分频数字锁相环（DPLL）的实现相关的技术，其包括与较高阶Σ-Δ匹配的环路响应。

27. 发明授权

US09473157B2 Frequency synthesizer with injection pulling/pushing suppression/mitigation and related frequency synthesizing method thereof 有权
标题翻译：具有注入拉/推抑制/抑制的频率合成器及其相关频率合成方法
公开(公告)号：US09473157B2
公开(公告)日：2016-10-18
申请号：US14339459
申请日：2014-07-24
申请人： MEDIATEK INC.
发明人： Chun-Ming Kuo , Chii-Horng Chen , Shih-Chi Shen , Ai-Hsuan Liu
IPC分类号： H03L7/16 , G04F10/00 , H03L7/099 , H03L7/107
CPC分类号： H03L7/16 , G04F10/005 , H03L7/099 , H03L7/1075 , H03L2207/50
摘要： A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.
摘要翻译：频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。

28. 发明申请

US20160065222A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160065222A1
公开(公告)日：2016-03-03
申请号：US14925570
申请日：2015-10-28
申请人： Renesas Electronics Corporation
发明人： Toshiharau OKAMOTO
IPC分类号： H03L7/08 , H03B5/32 , H03L7/16
CPC分类号： H03L7/0805 , H03B5/30 , H03B5/32 , H03B5/36 , H03L5/00 , H03L7/16
摘要： A semiconductor device includes a synthesizer, a phase locked loop (PLL) circuit, and a clock generating unit which is coupled to a crystal oscillator and generates an oscillation signal, and supplies the oscillation signal to the synthesizer and PLL circuit as a clock signal.
摘要翻译：半导体器件包括合成器，锁相环（PLL）电路和时钟产生单元，其耦合到晶体振荡器并产生振荡信号，并将振荡信号作为时钟信号提供给合成器和PLL电路。

29. 发明授权

US09036763B2 Methods and devices for implementing all-digital phase locked loop 有权
标题翻译：用于实现全数字锁相环的方法和装置
公开(公告)号：US09036763B2
公开(公告)日：2015-05-19
申请号：US13406342
申请日：2012-02-27
申请人： Olivier Burg , Miguel Kirsch
发明人： Olivier Burg , Miguel Kirsch
IPC分类号： H03D3/24 , H03L7/099 , H03L7/113 , H03L7/16
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
摘要翻译：全数字锁相环包括确定相位数的分数部分的时间到数字转换器。数字转换器的时间具有可能由相位噪声，延迟误差或偏斜误差引起的量化误差。若干方法和装置可以减少量化误差。噪声源可能在时间到数字转换器的输入处将抖动添加到参考时钟。数字处理器可以使用振荡器信号的两个连续的上升沿来计算到数字转换器到参考时钟的时间的时间延迟，并且使用这些计数来确定用于控制的振荡器信号的时间延迟和时间周期的比率数字控制振荡器。射频计数器电路检测振荡器信号是否由于偏斜引起或滞后于参考时钟，并产生相位信号以纠正偏斜。

30. 发明授权

US08994423B2 Phase-locked loop apparatus and method 有权
标题翻译：锁相环装置及方法
公开(公告)号：US08994423B2
公开(公告)日：2015-03-31
申请号：US14167852
申请日：2014-01-29
申请人： Julian Jenkins
发明人： Julian Jenkins
IPC分类号： H03L7/06 , H03L7/197 , H03L7/087 , H03L7/16
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/16 , H03L2207/50
摘要： A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency.
摘要翻译： PLL包括振荡器，时间 - 数字转换器（TDC）和用于剩余功能的系统。 TDC根据参考时钟测量振荡器的相位。测量相位具有从模数K计数器获得的整数部分和通过精细TDC测量的分数部分。该系统将测量的相位与期望的相位进行比较，并对其进行滤波以获得控制振荡器频率的参数。 TDC还可以包括同步块以对准精细TDC和脉冲隐藏器以减少由精细TDC使用的功率。该系统可以包括用于计算期望相位的整数部分的积分器，用于计算分数部分的第二积分器，以及用于更精细分数的内插器。获得快速锁定的方法包括使用相位误差率来控制振荡器频率。

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