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1. 发明授权

US06968029B1 Frequency prescaler 有权
标题翻译：频率预分频器
公开(公告)号：US06968029B1
公开(公告)日：2005-11-22
申请号：US10910731
申请日：2004-08-03
申请人： Chang-Hyeon Lee , Akbar Ali
发明人： Chang-Hyeon Lee , Akbar Ali
IPC分类号： H03K21/00 , H03K23/48
CPC分类号： H03K23/483
摘要： A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but may have a dead-zone period where it may fail to respond to a generated mode command. The dual modulus prescaler also has an output line that is synchronized to an extender section. The extender section is used to further divide the input signal, and is synchronized to an adjustable counter section. A sync controller circuit receives an output from the counter section, as well as a timing signal from the extender, and generates the mode signal on the mode command line. In this arrangement, the sync controller generates the mode signal at a time when the low order dual modulus is in a condition to change divide modes, thereby avoiding providing the signal during the dead-zone period.
摘要翻译：提供了一种同步预分频器，其具有用于接收与低阶双模预分频器同步的输入信号的输入线。双模预分频器通常根据模式命令行分隔，但可能具有死区周期，其中它可能无法响应生成的模式命令。双模预分频器还具有与扩展器部分同步的输出线。扩展器部分用于进一步分割输入信号，并与可调节的计数器部分同步。同步控制器电路接收来自计数器部分的输出以及来自延长器的定时信号，并在模式命令行上生成模式信号。在这种布置中，同步控制器在低阶双模量处于改变分频模式的条件下产生模式信号，从而避免在死区期间提供信号。

2. 发明授权

US4715052A Frequency divide by N circuit 失效
标题翻译：频率除N电路
公开(公告)号：US4715052A
公开(公告)日：1987-12-22
申请号：US838066
申请日：1986-03-10
申请人： Mark A. Stambaugh
发明人： Mark A. Stambaugh
IPC分类号： H03K23/44 , H03K23/48 , H03K21/10
CPC分类号： H03K23/44 , H03K23/483
摘要： A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.
摘要翻译：由n电路分频，其中n是奇数，其包括用于将频率“f”的输入时钟信号分成两个非重叠互补时钟信号“f”和移位寄存器电路的装置。移位寄存器电路耦合到信号分离装置，并且响应于两个互补时钟信号而产生频率为f / n的输出时钟信号。输出时钟信号具有等于（（n-1）/ 2 + Din）/ n的占空比，其中Din是输入时钟信号的占空比。输出占空比基本上与处理和操作条件无关。

3. 发明授权

US4369379A CMOS Frequency divider circuit having invalid signal override 失效
标题翻译： CMOS分频器电路具有无效的信号超驰
公开(公告)号：US4369379A
公开(公告)日：1983-01-18
申请号：US130299
申请日：1980-03-14
申请人： Charles G. Hull
发明人： Charles G. Hull
IPC分类号： H03K21/40 , H03K23/40 , H03K23/48 , H03K23/22 , H03K19/007 , H03K19/096
CPC分类号： H03K21/40 , H03K23/40 , H03K23/483
摘要： An improved CMOS frequency divider circuit is disclosed which has override logic for forcing the circuit to exit from a forbidden state to a valid state.
摘要翻译：公开了一种改进的CMOS分频器电路，其具有用于强制电路从禁止状态退出到有效状态的超控逻辑。

4. 发明授权

US3930169A Cmos odd multiple repetition rate divider circuit 失效
标题翻译： Cmos奇数倍重复分频电路
公开(公告)号：US3930169A
公开(公告)日：1975-12-30
申请号：US40149173
申请日：1973-09-27
申请人： MOTOROLA INC
发明人： KUHN JR HARRY A
IPC分类号： G04G3/02 , H03K3/037 , H03K23/46 , H03K23/48 , H03K23/08 , H03K3/33 , H03K19/08 , H03K21/36
CPC分类号： H03K23/483 , G04G3/022 , H03K3/0372 , H03K23/46
摘要： The disclosed divider circuit divides the repetition rate of an input signal by an odd integer to provide an output signal. The divider includes at least four binary cells and either a NOR and a NAND gate. Each binary cell includes first and second inversely clocked transmission gates and first and second inverters. Selected output terminals of three of the binary cells are connected to the input terminals of the gate and the output terminal of the gate is connected to the input terminal of the fourth binary cell. The resulting circuit configuration lends itself to fabrication by CMOS processes and takes up only a small amount of chip area.
摘要翻译：所公开的分频器电路将输入信号的重复率除以奇整数以提供输出信号。除法器包括至少四个二进制单元以及NOR和NAND门。每个二进制单元包括第一和第二反时钟传输门和第一和第二反相器。三个二进制单元的选择输出端子连接到栅极的输入端子，并且栅极的输出端子连接到第四个二进制单元的输入端子。所得到的电路结构适用于通过CMOS工艺制造，并且仅占用少量的芯片面积。

5. 发明授权

US10348316B2 Frequency division correction circuit, reception circuit, and integrated circuit 有权
公开(公告)号：US10348316B2
公开(公告)日：2019-07-09
申请号：US15656716
申请日：2017-07-21
申请人： SOCIONEXT INC.
发明人： Atsushi Matsuda
IPC分类号： H03K23/00 , H03L7/18 , H03K7/08 , H03L7/08 , H03K5/156 , H03K23/48 , H03L7/089 , H04L7/033
摘要： A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.

6. 发明授权

US09698800B2 System and method for clock generation with an output fractional frequency divider 有权
$System and method for clock generation with an output fractional frequency divider$
公开(公告)号：US09698800B2
公开(公告)日：2017-07-04
申请号：US14660711
申请日：2015-03-17
申请人： Linear Technology Corporation
发明人： Jan-Michael Stevenson
IPC分类号： H03L7/16 , H03K21/10 , H03K23/48
CPC分类号： H03L7/16 , H03K21/10 , H03K23/486
摘要： A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

7. 发明申请

US20060104405A1 High speed binary counter 有权
标题翻译：高速二进制计数器
公开(公告)号：US20060104405A1
公开(公告)日：2006-05-18
申请号：US10989504
申请日：2004-11-17
申请人： James Lewis
发明人： James Lewis
IPC分类号： H03K23/48
CPC分类号： H03K23/002
摘要： A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.
摘要翻译：高速二进制计数器包括用于每个二进制位的计数第一触发器，用于每个低位二进制位超过B 0和B 1的单个与门，以及每个高阶二进制位的至少两个与门。该计数器还包括一个输入因子延迟第二触发器。计数器还具有用于较低阶位的冗余最低有效项的机制。

8. 发明授权

US4692640A Majority circuit comprising binary counter 失效
标题翻译：多数电路包括二进制计数器
公开(公告)号：US4692640A
公开(公告)日：1987-09-08
申请号：US811449
申请日：1985-12-20
申请人： Seigo Suzuki , Yukihiko Yabe , Masumi Kawakami
发明人： Seigo Suzuki , Yukihiko Yabe , Masumi Kawakami
IPC分类号： H03K19/23 , H03K23/48
CPC分类号： H03K19/23
摘要： The majority circuit has an (n+1)/2-notation counter circuit comprising a plurality of cascade-connected binary counters. An odd number of n-bit serial data are counted by the counter circuit, and an output of the binary counter of the last stage is taken out as a majority output of the majority circuit.
摘要翻译：多数电路具有包括多个级联连接的二进制计数器的（n + 1）/ 2-符号计数器电路。通过计数器电路对奇数个n位串行数据进行计数，最后一级的二进制计数器的输出作为多数电路的多数输出。

9. 发明授权

US10447251B2 Power efficient high speed latch circuits and systems 有权
公开(公告)号：US10447251B2
公开(公告)日：2019-10-15
申请号：US15522052
申请日：2015-12-02
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Reza Bagger
IPC分类号： H03K3/356 , H03K3/3562 , H03K21/10 , H03K23/42 , H03K19/20 , H04B1/40 , H03K5/15 , H03K3/37 , H03K23/48
摘要： The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.

10. 发明授权

US10447250B2 Multi-stage frequency dividers and poly-phase signal generators 有权
公开(公告)号：US10447250B2
公开(公告)日：2019-10-15
申请号：US15522032
申请日：2015-12-02
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Reza Bagger
IPC分类号： H03K3/356 , H03K3/3562 , H03K21/10 , H03K23/42 , H03K19/20 , H04B1/40 , H03K5/15 , H03K3/37 , H03K23/48
摘要： An electronic latch circuit, a 4-phase signal generator, a multi-stage frequency divider and a poly-phase signal generator are disclosed. The electronic latch circuit comprises an output circuit comprising a first output and a second output. The electronic latch circuit further comprises an input circuit comprising a first input, a second input and a clock signal input. The electronic latch circuit is configured to change state based on the input signals' level at the inputs of the input circuit and a present state of the output circuit. The 4-phase signal generator is built with two electronic latch circuits. The multi-stage frequency dividers and poly-phase signal generators comprise a plurality of the electronic latch circuits and 4-phase signal generators.

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