专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09871533B2 Hybrid digital/analog noise shaping in the sigma-delta conversion 有权
公开(公告)号：US09871533B2
公开(公告)日：2018-01-16
申请号：US15421989
申请日：2017-02-01
申请人： Infineon Technologies AG
发明人： Igor Ullmann
IPC分类号： H03M1/06 , H03M3/00
CPC分类号： H03M3/352 , H03M3/358 , H03M3/414 , H03M3/454 , H03M3/458 , H03M7/3004
摘要： An analog/digital converter (ADC) includes an analog stage with at least one first sigma-delta modulator and includes a digital stage with at least one second sigma-delta modulator. The analog stage is configured for outputting a digital signal to the digital stage that is indicative of a noise contribution of the at least one first sigma-delta modulator. The analog stage and the digital stage may be arranged in a multi-stage noise shaping architecture (MASH) architecture.

2. 发明申请

US20160254823A1 ELECTRICAL CIRCUIT 有权
标题翻译：电路
公开(公告)号：US20160254823A1
公开(公告)日：2016-09-01
申请号：US15151236
申请日：2016-05-10
申请人： Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
发明人： Michael Hackner , Hans-Peter Hohe , Markus Sand
IPC分类号： H03M3/00 , H03L7/08
CPC分类号： H03M3/39 , H03L7/08 , H03M1/1255 , H03M1/50 , H03M1/82 , H03M3/462 , H03M3/496 , H03M3/50 , H03M7/3004
摘要： An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.
摘要翻译：电路包括信号处理链和控制器。所述信号处理链包括积分器，其被配置为在积分时间上积分输入信号。控制器连接到信号处理链的信号输出端，以接收和评估信号处理链的输出信号。控制器还被配置成基于输出信号调整积分时间。

3. 发明申请

US20150381188A1 HIGH-ORDER SIGMA DELTA FOR A DIVIDER-LESS DIGITAL PHASE-LOCKED LOOP 有权
标题翻译：高分辨率信号分割器，用于不带数字的数字锁相环
公开(公告)号：US20150381188A1
公开(公告)日：2015-12-31
申请号：US14317435
申请日：2014-06-27
申请人： Rotem Banin , Elan Banin , Ofir Degani
发明人： Rotem Banin , Elan Banin , Ofir Degani
IPC分类号： H03L7/085 , H03L7/083 , H04L7/033 , G04F10/00 , H03M3/00 , H04B1/40 , H03L7/08 , H03L7/099
CPC分类号： H03L7/085 , H03L7/16 , H03L2207/50 , H03M7/3004 , H04B1/40
摘要： Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
摘要翻译：这里描述的是与无分频数字锁相环（DPLL）的实现相关的技术，其包括与较高阶Σ-Δ匹配的环路响应。

4. 发明申请

US20140314178A1 DIGITAL WIRELESS TRANSMITTER HAVING PARALLEL STRUCTURE AND WIRELESS COMMUNICATION SYSTEM INCLUDING THE SAME 有权
标题翻译：具有并行结构和无线通信系统的数字无线发射机
公开(公告)号：US20140314178A1
公开(公告)日：2014-10-23
申请号：US14257518
申请日：2014-04-21
申请人： Sang-Ho Seo
发明人： Sang-Ho Seo
IPC分类号： H04B1/04 , H03M3/00 , H03M9/00
CPC分类号： H04B1/0475 , H03F3/24 , H03M3/30 , H03M3/508 , H03M7/3004 , H03M9/00 , H04B2001/0408
摘要： A digital wireless transmitter is provided. The digital wireless transmitter includes a serial-to-parallel converter, a delta-sigma modulator (DSM), and a radio frequency (RF) converter. The serial-to-parallel converter is configured to interpolate a serial digital input signal and to output N parallel signals, where N is a positive integer greater than one. The DSM is configured to perform delta-sigma modulation on the N parallel signals in parallel. The RF converter is configured to arrange N delta-sigma modulated signals into K parallel signals, to delay the K parallel signals by different delay times, and to convert delayed signals into an RF signal, where K is a positive integer greater than N.
摘要翻译：提供数字无线发射机。数字无线发射机包括串并转换器，Δ-Σ调制器（DSM）和射频（RF）转换器。串并转换器被配置为内插串行数字输入信号并输出N个并行信号，其中N是大于1的正整数。 DSM被配置为并行地对N个并行信号执行Δ-Σ调制。 RF转换器被配置为将N个Δ-Σ调制信号布置成K个并行信号，以将K个并行信号延迟不同的延迟时间，并将延迟的信号转换成RF信号，其中K是大于N的正整数。

5. 发明申请

US20100027711A1 DIGITAL LINEAR TRANSMITTER ARCHITECTURE 有权
标题翻译：数字线性发射机架构
公开(公告)号：US20100027711A1
公开(公告)日：2010-02-04
申请号：US12520486
申请日：2007-12-14
申请人： Tajinder Manku , Abdellatif Bellaouar
发明人： Tajinder Manku , Abdellatif Bellaouar
IPC分类号： H04L27/00 , H03M1/66
CPC分类号： H03M1/68 , H03M1/745 , H03M3/50 , H03M7/3004
摘要： A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (ΔΣ) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ΔΣ DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.
摘要翻译：一种用于数字到模拟转换射频信号的数字线性发射机。发射机在无线设备的发射路径中包括Δ西格玛（DeltaSigma）数模转换器（DAC）和加权信号数模转换器，以减少对相对大的模拟组件的依赖。 DeltaSigma DAC转换过采样信号的最低有效位，而加权信号数模转换器转换过采样信号的最高有效位。发射机核心包括用于提供过采样的调制数字信号的组件，然后在产生相应的模拟信号之前对过采样信号进行一阶滤波。该装置和方法减少了模拟组件并增加了无线RF设备的发射机核心架构中的数字组件。

6. 发明授权

US10840939B2 High efficiency power amplifier architectures for RF applications 有权
公开(公告)号：US10840939B2
公开(公告)日：2020-11-17
申请号：US16525066
申请日：2019-07-29
申请人： Mixed-Signal Devices Inc.
发明人： Tommy Yu , Avanindra Madisetti
IPC分类号： H03F3/38 , H03M3/00 , H03M7/32 , H03F1/02 , H03F3/24 , H03F3/19 , H03F3/217
CPC分类号： H03M3/39 , H03F1/0227 , H03F3/19 , H03F3/2171 , H03F3/245 , H03M7/3004 , H03F3/2175 , H03F2200/102 , H03F2200/171 , H03F2200/451
摘要： A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

7. 发明申请

US20180145700A1 High Efficiency Power Amplifier Architectures for RF Applications 审中-公开
公开(公告)号：US20180145700A1
公开(公告)日：2018-05-24
申请号：US15819475
申请日：2017-11-21
申请人： MY Tech, LLC
发明人： Tommy Yu , Avanindra Madisetti
IPC分类号： H03M3/00 , H03F3/217 , H03F3/19
CPC分类号： H03M3/39 , H03F1/0227 , H03F3/19 , H03F3/2171 , H03F3/2175 , H03F3/245 , H03F2200/102 , H03F2200/171 , H03F2200/451 , H03M7/3004
摘要： A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

8. 发明授权

US09589591B2 Signal processing device, signal processing method, and computer program 有权
标题翻译：信号处理装置，信号处理方法和计算机程序
公开(公告)号：US09589591B2
公开(公告)日：2017-03-07
申请号：US14534592
申请日：2014-11-06
申请人： SONY CORPORATION
发明人： Yuuki Matsumura , Shiro Suzuki
IPC分类号： G11B20/10 , H03M7/30 , H03M3/00 , G11B20/00
CPC分类号： G11B20/10037 , G11B20/10027 , G11B2020/00065 , H03M3/30 , H03M7/3004 , H03M7/3013 , H03M7/3031 , H03M7/3044 , H03M7/3048
摘要： There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by ΣΔ modulation and a second modulated signal obtained by subjecting the input signal to the ΣΔ modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.
摘要翻译：提供了一种信号处理装置，包括信号一致检测部分，其检测样本，其中基于比特出现次数的值在预设时段内在多个样本之间彼此重合的值在第一调制通过延迟通过ΣΔ调制获得的输入信号而获得的信号和通过再次对输入信号进行ΣΔ调制而获得的第二调制信号，在第一调制信号和第二调制信号之间切换以输出的信号切换部分，以及切换控制部分，其通过由信号重合检测部分获得的基于出现次数彼此重合的值的样本中的信号切换部分来控制第一调制信号和第二调制信号之间的切换。

9. 发明申请

US20170041019A1 DELTA SIGMA MODULATOR WITH DYNAMIC ERROR CANCELLATION 有权
标题翻译：具有动态错误消除的DELTA SIGMA调制器
公开(公告)号：US20170041019A1
公开(公告)日：2017-02-09
申请号：US15226436
申请日：2016-08-02
申请人： Texas Instruments Incorporated
发明人： Eeshan MIGLANI , Karthikeyan GUNASEKARAN , Santhosh Kumar GOWDHAMAN , Shagun DUSAD
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
摘要翻译：本公开提供了包括第一输入端口和第二输入端口的Δ-Σ调制器。这些端口接收差分输入信号。 DAC耦合到第一输入端口和第二输入端口，并且接收差分反馈信号和多个选择信号。环路滤波器响应差分误差信号产生差分滤波信号。差分误差信号与差分输入信号和差分反馈信号的差成比例。量化器响应于差分滤波信号产生量化的输出信号。耦合在量化器和DAC之间的经修改的DWA块响应于斩波时钟，规则时钟，量化的输出信号和多个选择索引信号产生多个选择信号。选择索引信号取决于先前生成的多个选择信号。

10. 发明授权

US09270288B2 Time-to-digital converter based on a voltage controlled oscillator 有权
标题翻译：基于压控振荡器的时间 - 数字转换器
公开(公告)号：US09270288B2
公开(公告)日：2016-02-23
申请号：US14448482
申请日：2014-07-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/093 , H03L7/08 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.
摘要翻译：锁相环（PLL）包括时间到电压转换器，以将参考信号和PLL的反馈信号之间的相位误差转换成一个或多个电压信号。基于振荡器的模数转换器（ADC）接收一个或多个电压信号，并根据电压控制一个或多个振荡器。基于振荡器的ADC基于一个或多个振荡器的频率来确定对应于相位误差的数字值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式