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21. 发明授权

US07012487B2 Transconductance device employing native MOS transistors 失效
公开(公告)号：US07012487B2
公开(公告)日：2006-03-14
申请号：US09837897
申请日：2001-04-18
申请人： Stephen Allott
发明人： Stephen Allott
IPC分类号： H03H11/00
CPC分类号： H03H11/42 , H03H11/0422
摘要： A system on chip such as a radio receiver has reduced suceptibility to voltages in the bulk silicon by using gyrator elements in the receiver with each gyrator element including a plurality of current sources interconnected to provide output transconductance voltages, and a variable load for the current sources including first and second load resistors each serially connected with one other plurality of current sources. A variable resistance interconnects nodes of the load resistors with the variable resistance comprising a pair of native MOS transistors having low threshold voltages. In a preferred embodiment the first and second load resistors comprise first and second MOS transistors with the pair of native transistors serially connected between source elements of the first and second MOS transistors.

22. 发明申请

US20060012451A1 Capacitive feedback circuit 失效
标题翻译：电容反馈电路
公开(公告)号：US20060012451A1
公开(公告)日：2006-01-19
申请号：US10520866
申请日：2003-06-25
申请人： Guillaume De Cremoux
发明人： Guillaume De Cremoux
IPC分类号： H03H11/00 , G05F3/16
CPC分类号： G05F1/46
摘要： An improved capacitive feedback circuit (20) comprises a feedback capacitor (23) having its output terminal connected to a high-impedance node (N). More particularly, the improved capacitive feedback circuit comprises a first branch (24) having a bias current source (25), an amplifying element (26), and a current sensor (27) connected in series, the amplifying element having a high-impedance control terminal (26c). The feedback capacitor (23) has its output terminal connected to said control terminal (26c). A current-to-voltage converting feedback loop (28) has a high-impedance output terminal (28c) connected to said feedback capacitor output terminal.
摘要翻译：改进的电容反馈电路（20）包括其输出端连接到高阻抗节点（N）的反馈电容器（23）。更具体地，改进的电容反馈电路包括具有偏置电流源（25）的第一分支（24），放大元件（26）和串联连接的电流传感器（27），放大元件具有高阻抗控制端子（26c）。反馈电容器（23）的输出端子连接到所述控制端子（26c）。电流 - 电压转换反馈环路（28）具有连接到所述反馈电容器输出端子的高阻抗输出端子（28c）。

23. 发明申请

US20050242906A1 Chua's circuit and it's use in a hyperchaotic circuit 有权
标题翻译：蔡氏的电路，它在超音速电路中使用
公开(公告)号：US20050242906A1
公开(公告)日：2005-11-03
申请号：US11036411
申请日：2005-01-14
申请人： Gaurav Gandhi
发明人： Gaurav Gandhi
IPC分类号： H03F1/34 , H03H11/00 , H03H11/52
CPC分类号： H03F1/34
摘要： The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.
摘要翻译：本发明提供了一种改进的蔡氏电路，其提供电流模式操作，访问所有状态变量，最少使用接地无源元件，并且不受无源元件匹配的影响，包括基于双输出电流输送器的电感器，其具有一个接地端子，所述电感器的第二端子，具有连接到所述电感器的第二端子的一个端子的电阻器，所述电阻器的第二端子连接到另一端接地的第二电容器的一个端子，以及一对双输出电流输送器连接在一起以形成具有一个端子连接到地的2端子负电阻，而第二端子连接到所述电阻的第二端子。

24. 发明申请

US20050134409A1 Chua's circuit and it's use in hyperchaotic circuit 审中-公开
标题翻译：蔡的电路，它在超线路电路中使用
公开(公告)号：US20050134409A1
公开(公告)日：2005-06-23
申请号：US10985327
申请日：2004-11-10
申请人： Gaurav Gandhi
发明人： Gaurav Gandhi
IPC分类号： H03F1/34 , H03H11/00 , H03H11/52
CPC分类号： H03F1/34
摘要： The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.
摘要翻译：本发明提供了一种改进的蔡氏电路，其提供电流模式操作，访问所有状态变量，最少使用接地无源元件，并且不受无源元件匹配的影响，包括基于双输出电流输送器的电感器，其具有一个接地端子，所述电感器的第二端子，具有连接到所述电感器的第二端子的一个端子的电阻器，所述电阻器的第二端子连接到另一端接地的第二电容器的一个端子，以及一对双输出电流输送器连接在一起以形成具有一个端子连接到地的2端子负电阻，而第二端子连接到所述电阻的第二端子。

25. 发明授权

US5710733A Processor-inclusive memory module 失效
公开(公告)号：US5710733A
公开(公告)日：1998-01-20
申请号：US589532
申请日：1996-01-22
申请人： David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
发明人： David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
IPC分类号： G06F15/78 , G11C5/00 , H01L25/18 , H05K7/14 , H03H11/00 , H05K7/02
CPC分类号： H05K7/1422 , G06F15/7864 , H01L25/18 , H01L2924/0002 , H01L2924/3011
摘要： A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.

26. 发明授权

US5424686A Negative-resistance-compensated microwave buffer 失效
标题翻译：负电阻补偿微波缓冲器
公开(公告)号：US5424686A
公开(公告)日：1995-06-13
申请号：US230351
申请日：1994-04-20
申请人： Stephen L. Wong , Jose M. Garcia
发明人： Stephen L. Wong , Jose M. Garcia
IPC分类号： H03F1/56 , H03F3/189 , H03F3/191 , H03H11/00
CPC分类号： H03F1/56
摘要： A monolithic microwave buffer amplifier is adapted to increase its input impedance at microwave frequencies. Capacitive reactances in first and second stages of the buffer amplifier appear collectively at the input of the first stage as a negative resistance. Compensating positive resistance is electrically connected to the input of the first stage to cancel the negative resistance and provide a sufficiently high resistive input impedance.
摘要翻译：单片微波缓冲放大器适于在微波频率下增加其输入阻抗。缓冲放大器的第一级和第二级的电容性电抗在第一级的输入处共同出现为负电阻。补偿正电阻电连接到第一级的输入以消除负电阻并提供足够高的电阻输入阻抗。

27. 发明授权

US5400003A Inherently impedance matched integrated circuit module 失效
标题翻译：固有阻抗匹配集成电路模块
公开(公告)号：US5400003A
公开(公告)日：1995-03-21
申请号：US105275
申请日：1993-08-12
申请人： Kenneth J. Kledzik
发明人： Kenneth J. Kledzik
IPC分类号： H01L23/64 , H01R24/50 , H05K1/02 , H05K1/14 , H05K3/30 , H05K7/02 , H03H11/00
CPC分类号： H01R24/50 , H01L23/64 , H05K7/023 , H01L2924/0002 , H01L2924/15312 , H01L2924/3011 , H01R2103/00 , H05K1/0237 , H05K1/144 , H05K3/308
摘要： A semiconductor circuit module is formed with external connections on coaxial pins. This provides a controlled impedance between a ground connection and a signal connection which is substantially equal per unit length. The module may be configured so that the impedance of the connection between the signal connections and integrated circuit may also be optimally impedance matched.
摘要翻译：在同轴引脚上形成有外部连接的半导体电路模块。这提供了接地连接和每单位长度基本上相等的信号连接之间的受控阻抗。模块可以被配置为使得信号连接和集成电路之间的连接的阻抗也可以被最佳地阻抗匹配。

28. 发明授权

US5349666A Reduced power line fluctuation/noise circuit by increasing impedance level when number of bus lines simultaneously change state exceeds the predetermined number 失效
标题翻译：当总线数量同时改变状态时，通过增加阻抗水平来减少电力线波动/噪声电路超过预定数量
公开(公告)号：US5349666A
公开(公告)日：1994-09-20
申请号：US838633
申请日：1992-02-20
申请人： Mitsuru Adachi , Tsunenori Umeki
发明人： Mitsuru Adachi , Tsunenori Umeki
IPC分类号： G06F13/00 , G06F1/26 , G06F3/00 , G06F15/78 , G08B21/00 , H03H11/00 , H03K5/08
CPC分类号： G06F1/26
摘要： A microcomputer that reduces through current of output buffers, and thus, reduces power line fluctuation that occurs when a large number of the bus lines connected to output buffers change state at the same time. The through current (or punch-through current) is reduced through the use of a detector circuit that detects the number of bus lines which are changing state and a decoder circuit that changes the impedance of output buffers, which drive the bus lines to external components, when the number of bus lines changing state at a given time exceeds a predetermined number.
摘要翻译：减少输出缓冲器电流的微型计算机，从而减少了当连接到输出缓冲器的大量总线线路同时改变状态时发生的电力线波动。通过使用检测正在改变状态的总线线路的检测器电路来减少直流电流（或穿通电流），以及改变输出缓冲器的阻抗的解码器电路，其将总线驱动到外部部件当在给定时间改变状态的总线数量超过预定数量时。

29. 发明授权

US5343170A Voltage controlled oscillator provided with negative feedback biasing 失效
标题翻译：压控振荡器提供负反馈偏置
公开(公告)号：US5343170A
公开(公告)日：1994-08-30
申请号：US2266
申请日：1993-01-08
申请人： Junseong Lee
发明人： Junseong Lee
IPC分类号： H03B7/00 , H03B1/00 , H03B1/04 , H03B5/00 , H03B5/20 , H03B5/24 , H03B7/06 , H03B27/00 , H03H11/46 , H03H11/52 , H03L7/099 , H03H11/00
CPC分类号： H03H11/46 , H03B5/24 , H03B7/06 , H03H11/52 , H03B1/04 , H03B2200/0058 , H03B2200/0062 , H03B2200/0092 , H03B2201/02 , H03B27/00 , H03B5/20
摘要： A voltage controlled oscillator (VCO) including a negative feedback circuit operates in response to a negative feedback signal generated during active transistor region operation of transistors in transconductance amplifying stages coupled thereto. As a result, harmonic distortion and problems of noise and unstable frequency oscillation are obviated or significantly reduced. The VCO includes first and second variable transconductance (gm) amplifying stages whose non-inverting (+) and inverting (-) terminals are respectively grounded and a first condenser connected between an output terminal of the first transconductance (gm) amplifying stage and a non-inverting (+) terminal of the second transconductance (gm) amplifying stage. A negative-resistive circuit is used to provide a negative feedback.
摘要翻译：包括负反馈电路的压控振荡器（VCO）响应于在与其耦合的跨导放大级中的晶体管的有源晶体管区域操作期间产生的负反馈信号而工作。结果，谐波失真和噪声问题以及不稳定的频率振荡被消除或显着减少。 VCO包括第一和第二可变跨导（gm）放大级，其非反相（+）和反相（ - ）端分别接地，并且第一电容器连接在第一跨导（gm）放大级的输出端和非反相 - 第二跨导（gm）放大级的（+）端子。负电阻电路用于提供负反馈。

30. 发明授权

US5315162A Electrochemical synapses for artificial neural networks 失效
标题翻译：人工神经网络的电化学突触
公开(公告)号：US5315162A
公开(公告)日：1994-05-24
申请号：US770817
申请日：1991-10-04
申请人： John McHardy , Carl W. Townsend , Lin R. Higley , Frank A. Ludwig
发明人： John McHardy , Carl W. Townsend , Lin R. Higley , Frank A. Ludwig
IPC分类号： G06N3/063 , G06G7/06 , H03H11/00
CPC分类号： G06N3/0635
摘要： An electrochemical synapse adapted for use in a neural network which includes an input terminal and an output terminal located at a distance of less than 100 microns from the input terminal. A permanent interconnect having controllable conductivity is located between the two inputs. The conductivity of the permanent interconnect is controlled by either growing or eliminating metallic whiskers between the inputs. The growth and elimination of whiskers provides a rapid and controllable electrochemical synapse. Partial neural network systems are disclosed utilizing the electrochemical synapse.
摘要翻译：一种适用于神经网络的电化学突触，其包括位于离输入端子小于100微米距离的输入端子和输出端子。具有可控导电性的永久互连位于两个输入之间。通过在输入之间生长或消除金属晶须来控制永久互连的导电性。晶须的生长和消除提供了快速和可控的电化学突触。利用电化学突触公开了部分神经网络系统。

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