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31. 发明申请

US20060064518A1 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US20060064518A1
公开(公告)日：2006-03-23
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

32. 发明授权

US09934079B2 Fast remote communication and computation between processors using store and load operations on direct core-to-core memory 有权
公开(公告)号：US09934079B2
公开(公告)日：2018-04-03
申请号：US12789082
申请日：2010-05-27
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
IPC分类号： G06F15/00 , G06F15/76 , G06F9/54
CPC分类号： G06F9/544
摘要： A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.

33. 发明授权

US09009716B2 Creating a thread of execution in a computer processor 有权
标题翻译：在计算机处理器中创建执行线程
公开(公告)号：US09009716B2
公开(公告)日：2015-04-14
申请号：US13458781
申请日：2012-04-27
申请人： Patrick J. Bohrer , Ahmed Gheith , James L. Peterson
发明人： Patrick J. Bohrer , Ahmed Gheith , James L. Peterson
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4843
摘要： Creating a thread of execution in a computer processor, including copying, as indicated by a hardware processor opcode having been specified by a user-level process, data from a first set of registers to a second set of registers, wherein the first set of registers is associated with a parent hardware thread, wherein the second set of registers is associated with a child hardware thread, wherein the child hardware thread is in a wait state, and changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.
摘要翻译：在计算机处理器中创建执行线程，包括由用户级过程指定的硬件处理器操作码所指示的复制，从第一组寄存器到第二组寄存器的数据，其中第一组寄存器与父硬件线程相关联，其中所述第二组寄存器与子硬件线程相关联，其中所述子硬件线程处于等待状态，并且如硬件处理器操作码所指示的，从所述子硬件线程等待状态到短暂的运行状态。

34. 发明申请

US20120317234A1 MANAGING DATA ACCESS IN MOBILE DEVICES 审中-公开
标题翻译：在移动设备中管理数据访问
公开(公告)号：US20120317234A1
公开(公告)日：2012-12-13
申请号：US13156795
申请日：2011-06-09
申请人： Patrick Joseph BOHRER , Ahmed GHEITH , James Lyle PETERSON
发明人： Patrick Joseph BOHRER , Ahmed GHEITH , James Lyle PETERSON
IPC分类号： G06F15/16
CPC分类号： H04W4/00
摘要： A, system, and computer program product for managing data access in a mobile device are provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.
摘要翻译：在说明性实施例中提供了用于管理移动设备中的数据访问的A，系统和计算机程序产品。使用在移动设备中执行的数据管理器，在数据模型中配置数据项。数据项的值参数用数据填充，数据项的状态参数填充状态指示。从在移动设备中执行的移动应用接收对数据项的订阅。响应于订阅，数据项的数据和状态被发送到移动应用。

35. 发明申请

US20120317228A1 MANAGING DATA ACCESS IN MOBILE DEVICES 审中-公开
标题翻译：在移动设备中管理数据访问
公开(公告)号：US20120317228A1
公开(公告)日：2012-12-13
申请号：US13459779
申请日：2012-04-30
申请人： PATRICK JOSEPH BOHRER , AHMED GHEITH , JAMES LYLE PETERSON
发明人： PATRICK JOSEPH BOHRER , AHMED GHEITH , JAMES LYLE PETERSON
IPC分类号： G06F15/16
CPC分类号： H04W4/00
摘要： A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.
摘要翻译：在说明性实施例中提供了一种用于在移动设备中管理数据访问的方法。使用在移动设备中执行的数据管理器，在数据模型中配置数据项。数据项的值参数用数据填充，数据项的状态参数填充状态指示。从在移动设备中执行的移动应用接收对数据项的订阅。响应于订阅，数据项的数据和状态被发送到移动应用。

36. 发明申请

US20120216204A1 CREATING A THREAD OF EXECUTION IN A COMPUTER PROCESSOR 有权
标题翻译：在计算机处理器中创建执行螺纹
公开(公告)号：US20120216204A1
公开(公告)日：2012-08-23
申请号：US13458781
申请日：2012-04-27
申请人： Patrick J. Bohrer , Ahmed Gheith , James L. Peterson
发明人： Patrick J. Bohrer , Ahmed Gheith , James L. Peterson
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： Creating a thread of execution in a computer processor, including copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state, and changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.
摘要翻译：在计算机处理器中创建执行线程，包括由没有操作系统参与的由用户级进程调用的硬件处理器操作码复制，将内容从父硬件线程注册到子硬件线程，子硬件线程为处于等待状态，并且通过硬件处理器操作码将子硬件线程从等待状态改变为短暂运行状态。

37. 发明申请

US20110265068A1 Single Thread Performance in an In-Order Multi-Threaded Processor 失效
标题翻译：单线程处理器中的单线程性能
公开(公告)号：US20110265068A1
公开(公告)日：2011-10-27
申请号：US12767886
申请日：2010-04-27
申请人： Elmootazbellah N. Elnozahy , Ahmed Gheith
发明人： Elmootazbellah N. Elnozahy , Ahmed Gheith
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A mechanism is provided for improving single-thread performance for a multi-threaded, in-order processor core. In a first phase, a compiler analyzes application code to identify instructions that can be executed in parallel with focus on instruction-level parallelism and removing any register interference between the threads. The compiler inserts as appropriate synchronization instructions supported by the apparatus to ensure that the resulting execution of the threads is equivalent to the execution of the application code in a single thread. In a second phase, an operating system schedules the threads produced in the first phase on the hardware threads of a single processor core such that they execute simultaneously. In a third phase, the microprocessor core executes the threads specified by the second phase such that there is one hardware thread executing an application thread.
摘要翻译：提供了一种用于提高多线程，按顺序处理器内核的单线程性能的机制。在第一阶段，编译器分析应用程序代码以识别可以并行执行的指令，重点是指令级并行性，并消除线程之间的任何寄存器干扰。编译器插入作为设备支持的适当的同步指令，以确保线程的结果执行等同于单个线程中应用程序代码的执行。在第二阶段中，操作系统在单个处理器核心的硬件线程上调度在第一阶段产生的线程，使得它们同时执行。在第三阶段，微处理器核心执行由第二阶段指定的线程，使得有一个硬件线程执行应用程序线程。

38. 发明申请

US20110258421A1 Architecture Support for Debugging Multithreaded Code 审中-公开
标题翻译：架构支持调试多线程代码
公开(公告)号：US20110258421A1
公开(公告)日：2011-10-20
申请号：US12762817
申请日：2010-04-19
申请人： Elmootazbellah N. Elnozahy , Ahmed Gheith
发明人： Elmootazbellah N. Elnozahy , Ahmed Gheith
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F9/3824 , G06F11/3636 , G06F11/3648
摘要： Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
摘要翻译：提供了使用内容可寻址存储器调试应用程序代码的机制。机构在数据处理系统的处理器的硬件单元中接收指令，该指令具有指令试图访问的目标存储器地址。搜索与硬件单元相关联的内容可寻址存储器（CAM），以对应于目标存储器地址的CAM中的条目。响应于与所找到的目标存储器地址相对应的CAM中的条目，确定条目中的信息是否将该指令识别为感兴趣的指令。响应于将该指令识别为感兴趣的指令的条目，生成异常并将其发送到异常处理程序或调试器应用程序之一。以这种方式，可以以有效的方式执行多线程应用程序的调试。

39. 发明申请

US20060230409A1 Multithreaded processor architecture with implicit granularity adaptation 审中-公开
标题翻译：具有隐式粒度适配性的多线程处理器架构
公开(公告)号：US20060230409A1
公开(公告)日：2006-10-12
申请号：US11101608
申请日：2005-04-07
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new threads and having a novel operational semantics. If a hardware thread is available to shepherd a forked thread, the fork and join instructions have thread creation and termination/synchronization semantics, respectively. If no hardware thread is available, however, the fork and join instructions assume subroutine call and return semantics respectively. The link register of the processor is used to determine whether a given join instruction should be treated as a thread synchronization operation or as a return from subroutine operation.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新线程并具有新颖的操作语义的“叉”和“连接”指令。如果一个硬件线程可用于分派叉形线程，则fork和join指令分别具有线程创建和终止/同步语义。然而，如果没有硬件线程可用，fork和join指令分别假定子程序调用和返回语义。处理器的链接寄存器用于确定给定的连接指令是否应被视为线程同步操作或作为从子程序操作返回。

40. 发明申请

US20060230408A1 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US20060230408A1
公开(公告)日：2006-10-12
申请号：US11101601
申请日：2005-04-07
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/46
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

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