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31. 发明授权

US08234652B2 Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks 有权
标题翻译：执行设置操作以在处理器执行消息传递接口任务时接收不同数量的数据
公开(公告)号：US08234652B2
公开(公告)日：2012-07-31
申请号：US11846154
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： Mechanisms are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so us to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译：提供了用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数据量的设置操作的机制。提供了用于调整处理器的处理工作负载的平衡的机制，使得我们最小化等待所有处理器调用同步操作的等待周期。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

32. 发明授权

US08214603B2 Method and apparatus for handling multiple memory requests within a multiprocessor system 有权
标题翻译：用于在多处理器系统内处理多个存储器请求的方法和装置
公开(公告)号：US08214603B2
公开(公告)日：2012-07-03
申请号：US12024181
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译：公开了一种在多处理器系统内处理多个存储器请求的方法。锁控制部分最初被分配给系统存储器内的数据块。响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。

33. 发明授权

US08200910B2 Generating and issuing global shared memory operations via a send FIFO 有权
标题翻译：通过发送FIFO生成和发出全局共享内存操作
公开(公告)号：US08200910B2
公开(公告)日：2012-06-12
申请号：US12024664
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F9/544
摘要： A method for issuing global shared memory (GSM) operations from an originating task on a first node coupled to a network fabric of a distributed network via a host fabric interface (HFI). The originating task generates a GSM command within an effective address (EA) space. The task then places the GSM command within a send FIFO. The send FIFO is a portion of real memory having real addresses (RA) that are memory mapped to EAs of a globally executing job. The originating task maintains a local EA-to-RA mapping of only a portion of the real address space of the globally executing job. The task enables the HFI to retrieve the GSM command from the send FIFO into an HFI window allocated to the originating task. The HFI window generates a corresponding GSM packet containing GSM operations and/or data, and the HFI window issues the GSM packet to the network fabric.
摘要翻译：一种用于通过主机结构接口（HFI）从耦合到分布式网络的网络结构的第一节点上的始发任务发出全局共享存储器（GSM）操作的方法。始发任务在有效地址（EA）空间内生成GSM命令。然后任务将GSM命令放在发送FIFO中。发送FIFO是具有存储器映射到全局执行作业的EA的实际地址（RA）的实际存储器的一部分。始发任务维护仅全局执行作业的实际地址空间的一部分的本地EA到RA映射。该任务使HFI能够将GSM命令从发送FIFO检索到分配给始发任务的HFI窗口中。 HFI窗口产生包含GSM操作和/或数据的相应的GSM分组，并且HFI窗口向网络结构发出GSM分组。

34. 发明授权

US07996564B2 Remote asynchronous data mover 失效
标题翻译：远程异步数据移动器
公开(公告)号：US07996564B2
公开(公告)日：2011-08-09
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译：分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问数据中心为远程存储器的节点ID。

35. 发明授权

US07958183B2 Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture 失效
标题翻译：使用多层全图互连体系结构中叶节点的软件设置和部分软件执行来执行集体操作
公开(公告)号：US07958183B2
公开(公告)日：2011-06-07
申请号：US11845224
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A mechanism for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In software executing on the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译：执行集体行动的机制。在第一处理器书中在母处理器上执行的软件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包含该父处理器和其他处理器。在在母处理器上执行的软件中，多个处理器在逻辑上被布置为分层结构中的多个节点。基于层次结构将集体操作发送到多个处理器。在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。

36. 发明授权

US07877436B2 Mechanism to provide reliability through packet drop detection 失效
标题翻译：通过分组丢包检测提供可靠性的机制
公开(公告)号：US07877436B2
公开(公告)日：2011-01-25
申请号：US12024600
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F9/544
摘要： A method and a data processing system for completing checkpoint processing of a distributed job with local tasks communicating with other remote tasks via a host fabric interface (HFI) and assigned HFI window. Each HFI window has a send count and a receive count, which tracks GSM messages that are sent from and received at the HFI window. When a checkpoint is initiated by a master task, each local task forwards the send count and the receive count to the master task. The master task sums the respective counts and then compares the totals to each other. When the send count total is equal to the receive count total, the tasks are permitted to continue processing. However, when the send count total is not equal to the receive count total, the master task notifies each task of the job to rollback to a previous checkpoint or kill the job execution.
摘要翻译：一种方法和数据处理系统，用于通过主机结构接口（HFI）和分配的HFI窗口完成与其他远程任务通信的本地任务的分布式作业的检查点处理。每个HFI窗口都有发送计数和接收计数，用于跟踪在HFI窗口发送和接收的GSM消息。当主任务启动检查点时，每个本地任务将发送计数和接收计数转发给主任务。主任务对各个计数进行相加，然后将总计相互比较。当发送计数总数等于接收计数总数时，允许任务继续处理。但是，当发送计数总数不等于接收计数总数时，主任务会通知作业的每个任务以回滚到先前的检查点或终止作业执行。

37. 发明授权

US07873879B2 Mechanism to perform debugging of global shared memory (GSM) operations 失效
标题翻译：执行全局共享内存（GSM）操作调试的机制
公开(公告)号：US07873879B2
公开(公告)日：2011-01-18
申请号：US12024585
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F11/00
CPC分类号： G06F13/385
摘要： A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.
摘要翻译：主机结构接口（HFI）可以调试从网络结构在本地节点接收到的全局共享存储器（GSM）操作。本地节点具有存储器管理单元（MMU），该存储器管理单元（MMU）为HFI用于实际地址（EA-to-RA）转换表提供有效地址，以评估来自接收到的GSM分组的GSM操作/数据的EAs是否为内存映射到本地内存的RA。 HFI检索与接收的GSM分组内的GSM操作/数据相关联的EA。 HFI将EA转发到MMU，该MMU确定EA何时映射到本地内存中的本地任务的RA。 HFI处理逻辑仅当GSM操作的EA / GSM分组内的数据是具有本地RA转换的EA时才能处理GSM分组。不匹配的EA会导致需要调试的错误条件。

38. 发明授权

US07827428B2 System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权
标题翻译：用于在多层全图互连架构中提供集群范围的系统时钟的系统
公开(公告)号：US07827428B2
公开(公告)日：2010-11-02
申请号：US11848440
申请日：2007-08-31
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12
CPC分类号： G06F1/12 , H04J3/0685 , H04Q2213/13092 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/1336
摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译：提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。计算群集中的每个处理器芯片发送的心跳信号同步。基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

39. 发明授权

US07822889B2 Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture 失效
标题翻译：使用多层全图互连架构直接/间接传输信息
公开(公告)号：US07822889B2
公开(公告)日：2010-10-26
申请号：US11845209
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F3/00
CPC分类号： G06F13/387
摘要： A mechanism is provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link.
摘要翻译：提供了用于在数据网络中传输数据的机制。数据网络的第一处理器接收要发送到数据网络内的第二处理器的数据。如果数据先前已经通过源处理器的间接通信链路被路由，则确定是间接通信链路是不直接将源处理器耦合到要接收数据的最终目的地处理器的通信链路。基于确定数据是否已经通过间接通信链路路由的结果，选择通信链路来将数据从第一处理器传送到第二处理器。最后，使用所选择的通信链路将数据从第一处理器发送到第二处理器。

40. 发明申请

US20100268788A1 Remote Asynchronous Data Mover 失效
标题翻译：远程异步数据移动器
公开(公告)号：US20100268788A1
公开(公告)日：2010-10-21
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F15/167 , G06F9/46 , G06F12/00 , G06F12/10
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译：分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问数据中心为远程存储器的节点ID。

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