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31. 发明申请

US20190324724A1 Geometric Synthesis 审中-公开
公开(公告)号：US20190324724A1
公开(公告)日：2019-10-24
申请号：US16457094
申请日：2019-06-28
申请人： Sergey Vladimirovich Gribok , Gregg William Baeckler , Martin Langhammer
发明人： Sergey Vladimirovich Gribok , Gregg William Baeckler , Martin Langhammer
IPC分类号： G06F7/501 , G06F17/50 , G06F17/11
摘要： A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

32. 发明申请

US20190318058A1 High Performance Regularized Network-on-Chip Architecture 审中-公开
公开(公告)号：US20190318058A1
公开(公告)日：2019-10-17
申请号：US16457114
申请日：2019-06-28
申请人： Gregg William Baeckler , Martin Langhammer , Sergey Vladimirovich Gribok
发明人： Gregg William Baeckler , Martin Langhammer , Sergey Vladimirovich Gribok
IPC分类号： G06F17/50
摘要： Techniques for designing and implementing networks-on-chip (NoCs) are provided. For example, a computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit includes determining a first portion of a plurality of registers to potentially be included in a NoC design, determining routing information regarding datapaths between registers of the first portion of the plurality of registers, and determining an expected performance associated with the first portion of the plurality of registers. The method also includes determining whether the expected performance is within a threshold range, including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range, and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit.

33. 发明授权

US09170775B2 Flexible accumulator in digital signal processing circuitry 有权
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US09170775B2
公开(公告)日：2015-10-27
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

34. 发明授权

US08996600B1 Specialized processing block for implementing floating-point multiplier with subnormal operation support 有权
标题翻译：专用处理块用于实现具有异常运算支持的浮点乘法器
公开(公告)号：US08996600B1
公开(公告)日：2015-03-31
申请号：US13566256
申请日：2012-08-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/487 , G06F7/485
CPC分类号： G06F7/485 , G06F7/4876 , G06F7/49915
摘要： The functions available in a specialized processing block of a programmable device include floating-point operations, including support within the specialized processing block for subnormal operations. This is accomplished, in part, by borrowing an adder in the specialized processing block and using the adder to operate on output of a multiplier or other operator to compete a subnormal operation. Although the adder becomes unavailable to serve as an adder, the need to complete the operation in slower, more valuable general purpose logic is avoided. The adder and the other operator need not necessarily be located together in a specialized processing block.
摘要翻译：可编程设备的专用处理块中可用的功能包括浮点运算，包括在专用处理块内用于次正常运算的支持。这部分地通过借用专用处理块中的加法器并且使用加法器对乘法器或其他运算符的输出进行操作来竞争次正常操作来实现。虽然加法器不可用作加法器，但是避免了以较慢，更有价值的通用逻辑完成操作的需要。加法器和其他操作器不必一定位于专门的处理块中。

35. 发明授权

US08949298B1 Computing floating-point polynomials in an integrated circuit device 有权
标题翻译：计算集成电路器件中的浮点多项式
公开(公告)号：US08949298B1
公开(公告)日：2015-02-03
申请号：US13234419
申请日：2011-09-16
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/00
CPC分类号： G06F7/552 , G06F7/483 , G06F7/548 , G06F2207/5523
摘要： Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, where the input variable has a mantissa and an exponent, and the circuitry has a number of bits of precision, includes multiplier circuitry that calculates a common power of the input variable factored out of terms of the polynomial having powers of the variable greater than 1. The polynomial circuitry further includes, for each respective remaining term of the polynomial that contributes to the number of bits of precision: (1) a coefficient memory loaded with a plurality of instances of a coefficient for the respective term, each instance being shifted by a different number of bits, (2) address circuitry for selecting one of the instances of the coefficient based on the exponent, and (3) circuitry for combining the selected instance of the coefficient with a corresponding power of the input variable to compute the respective term.
摘要翻译：用于计算具有包括输入变量的功率的项的多项式的多项式电路，其中所述输入变量具有尾数和指数，并且所述电路具有多个精度位，所述多项式电路包括计算所述输入变量的公共功率的乘法器电路对于具有大于1的变量的幂的多项式的项，多项式电路还包括对有助于精度位数的多项式的每个相应剩余项：（1）加载多个用于各个术语的系数的实例，每个实例被移位不同位数，（2）用于基于指数选择系数的一个实例的地址电路，以及（3）用于组合所选择的实例的电路该系数具有输入变量的相应功率以计算相应的项。

36. 发明授权

US08898551B1 Reduced matrix Reed-Solomon encoding 有权
标题翻译：减少矩阵里德 - 所罗门编码
公开(公告)号：US08898551B1
公开(公告)日：2014-11-25
申请号：US13530683
申请日：2012-06-22
申请人： Martin Langhammer , Daniel Elphick
发明人： Martin Langhammer , Daniel Elphick
IPC分类号： H03M13/15
CPC分类号： H03M13/1515 , H03M13/15 , H03M13/611 , H03M13/616 , H03M13/6502
摘要： In an arrangement of the disclosed systems, devices, and methods, a matrix representation of a block code comprising m bit-planes is obtained, a generator matrix corresponding to each of the m bit-planes from the matrix representation is extracted, a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code are determined, a reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are determined, and instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are generated.
摘要翻译：在公开的系统，装置和方法的布置中，获得包括m个位平面的块码的矩阵表示，提取与矩阵表示中的每个m位平面对应的生成矩阵，变换后的生成器矩阵和用于块码的第一比特平面的经变换的数据符号向量，确定通过块码的第m位平面的第二位平面中的每一个的反向映射变换的生成器矩阵，以及指令生成基于用于第一位平面的经变换的生成矩阵和通过块代码的第m位平面的第二位平面中的每一个的反向映射变换的生成器矩阵的编码器架构。

37. 发明授权

US08826038B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08826038B1
公开(公告)日：2014-09-02
申请号：US13474745
申请日：2012-05-18
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F21/00
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

38. 发明授权

US08805911B1 Cholesky decomposition in an integrated circuit device 有权
标题翻译：集成电路器件中的Cholesky分解
公开(公告)号：US08805911B1
公开(公告)日：2014-08-12
申请号：US13149661
申请日：2011-05-31
申请人： Lei Xu , Martin Langhammer
发明人： Lei Xu , Martin Langhammer
IPC分类号： G06F7/38
CPC分类号： G06F17/16
摘要： Efficient and scalable circuitry for performing Cholesky decomposition is based on two types of processing elements. A first type of processing element provides inverse square root and multiplication operations. A second type of processing element includes a first computation path for outputting an inner product difference element and a second computation path for outputting an inner product element. Processing elements of the first and second type may be cascaded to achieve a decomposition of a matrix of an arbitrary size. The circuitry is flexible to allow different throughput requirements, and can be optimized to reduce latency and resource consumption.
摘要翻译：用于执行Cholesky分解的高效和可扩展的电路基于两种类型的处理元件。第一类处理元件提供反平方根和乘法运算。第二类型的处理元件包括用于输出内积差元件的第一计算路径和用于输出内积元件的第二计算路径。可以级联第一和第二类型的处理元件以实现任意大小的矩阵的分解。该电路是灵活的，以允许不同的吞吐量要求，并且可以被优化以减少延迟和资源消耗。

39. 发明授权

US08645451B2 Double-clocked specialized processing block in an integrated circuit device 有权
标题翻译：集成电路设备中的双时钟专用处理模块
公开(公告)号：US08645451B2
公开(公告)日：2014-02-04
申请号：US13044680
申请日：2011-03-10
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/523
CPC分类号： G06F7/5324
摘要： Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products.
摘要翻译：可以在固定逻辑器件中提供用于将乘法器的精度提高所需因数的电路，同时将乘法器的算术复杂度的增加限制为固定逻辑器件，或者可以配置成可编程集成电路器件，例如可编程逻辑器件（ PLD）。算术复杂度的增加较小，因此，通过在交替的时钟周期中不同地使用专门的处理块组件来实现增加与精度的增加成比例，而不是精度增加的平方。例如，要实现双精度，在两个时钟周期的每一个中使用相同的乘法器组件，但是在两个周期中使用了一些专门的处理块内部结构（例如，移位器和加法器），因此在两个周期中，可以从较小的部分乘积计算较大的乘积。

40. 发明授权

US08412756B1 Multi-operand floating point operations in a programmable integrated circuit device 有权
标题翻译：可编程集成电路器件中的多操作数浮点运算
公开(公告)号：US08412756B1
公开(公告)日：2013-04-02
申请号：US12557952
申请日：2009-09-11
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F7/5095 , G06F7/485
摘要： A programmable logic device is programmed to add a plurality N of unnormalized numbers at once. Because the inputs are not normalized, they could all have different exponents. The largest exponent of the N exponents is found, and for each of the inputs, its mantissa is right-shifted at by the difference between the largest exponent and the exponent of that particular input. The N shifted mantissas are combined, optionally with sign data, in an (N+1):2 compressor to provide carry and save vectors which may be combined in a carry-propagate adder. Numbers may converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.
摘要翻译：可编程逻辑器件被编程为一次添加多个N个非标准化数字。由于输入不正则化，它们都可能具有不同的指数。找到N个指数的最大指数，并且对于每个输入，其尾数通过最大指数和该特定输入的指数之间的差进行右移。 N个移位尾数与（N + 1）：2压缩器中的符号数据可选地组合，以提供携带和保存向量，其可以组合在进位传播加法器中。数字可能会在操作结束时转换回规范化形式。如果需要避免数据丢失，可以在中间步骤之后对数字进行归一化。

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