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1. 发明授权

US08826038B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08826038B1
公开(公告)日：2014-09-02
申请号：US13474745
申请日：2012-05-18
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F21/00
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

2. 发明授权

US08209545B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08209545B1
公开(公告)日：2012-06-26
申请号：US12785400
申请日：2010-05-21
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： H04L9/08
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

3. 发明授权

US07725738B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US07725738B1
公开(公告)日：2010-05-25
申请号：US11042477
申请日：2005-01-25
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F12/14
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

4. 发明授权

US07228451B1 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit 有权
标题翻译：可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
公开(公告)号：US07228451B1
公开(公告)日：2007-06-05
申请号：US11270801
申请日：2005-11-08
申请人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
发明人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
摘要翻译：用于集成电路的时钟网络包括被配置为将时钟信号分配给集成电路的第一部分的第一组线路。时钟网络还包括第二组线路，其被配置为将时钟信号分配给集成电路的第一部分与集成电路的第二部分分开。

5. 发明授权

US06996736B1 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit 有权
标题翻译：可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
公开(公告)号：US06996736B1
公开(公告)日：2006-02-07
申请号：US10076172
申请日：2002-02-12
申请人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
发明人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
摘要翻译：用于集成电路的时钟网络包括被配置为将时钟信号分配给集成电路的第一部分的第一组线路。时钟网络还包括第二组线路，其被配置为将时钟信号分配给集成电路的第一部分与集成电路的第二部分分开。

6. 发明授权

US07161381B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US07161381B1
公开(公告)日：2007-01-09
申请号：US10787818
申请日：2004-02-25
申请人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
发明人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/1776
摘要： A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
摘要翻译：可编程逻辑器件（PLD）包括第一存储器块和至少第二存储器块，其中两个存储器块具有不同的存储器大小。

7. 发明授权

US07051153B1 Memory array operating as a shift register 有权
标题翻译：存储器阵列作为移位寄存器
公开(公告)号：US07051153B1
公开(公告)日：2006-05-23
申请号：US10140312
申请日：2002-05-06
申请人： Yi-Wen Lin , Changsong Zhang , David Jefferson , Srinivas Reddy
发明人： Yi-Wen Lin , Changsong Zhang , David Jefferson , Srinivas Reddy
IPC分类号： G06F12/00
CPC分类号： G11C19/38
摘要： A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected between the output of the first column of memory cells and the input of the second column of memory cells. The memory array can be operated as a shift register by shifting data from the first column of memory cells to the second column of memory cells through the multiplexer rather than using general routing lines.
摘要翻译：配置为作为移位寄存器操作的存储器阵列包括具有输入和输出的第一列存储器单元和具有输入和输出的至少第二列存储器单元。存储器阵列还包括连接在第一列存储器单元的输出和第二列存储单元的输入之间的多路复用器。存储器阵列可以通过多路复用器将数据从第一列存储器单元移位到第二列而不是使用一般路由线来作为移位寄存器来操作。

8. 发明授权

US6094064A Programmable logic device incorporating and input/output overflow bus 失效
标题翻译：可编程逻辑器件并入和输入/输出溢出总线
公开(公告)号：US6094064A
公开(公告)日：2000-07-25
申请号：US121250
申请日：1998-07-23
申请人： Manuel Mejia , David Jefferson , Srinivas Reddy
发明人： Manuel Mejia , David Jefferson , Srinivas Reddy
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/1736
摘要： A programmable logic device architecture incorporating a peripheral overflow bus is disclosed. In a preferred embodiment, the programmable logic device has a core region that includes at least a plurality of logic cells interconnected by way of associated programmable logic cell conductors. The interconnected logic cells form an array suitable for use in implementing desired logic functions. The programmable logic device also has a peripheral region. The peripheral region includes at least a plurality of bi-directional ports of which selected ones may be coupled to external circuitry. The peripheral region also includes a bi-directional peripheral I/O overflow bus suitably arranged to pass a plurality of control signals and a plurality of data signals between the core region and the plurality of bi-directional ports.
摘要翻译：公开了一种结合外设溢出总线的可编程逻辑器件架构。在优选实施例中，可编程逻辑器件具有核心区域，其包括通过相关联的可编程逻辑单元导体互连的至少多个逻辑单元。互连的逻辑单元形成适合用于实现期望的逻辑功能的阵列。可编程逻辑器件还具有外围区域。外围区域包括至少多个双向端口，其中所选择的端口可以耦合到外部电路。外围区域还包括适当地布置成在核心区域和多个双向端口之间传递多个控制信号和多个数据信号的双向外围I / O溢出总线。

9. 发明授权

US06720796B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US06720796B1
公开(公告)日：2004-04-13
申请号：US10140311
申请日：2002-05-06
申请人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
发明人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
IPC分类号： H03K19177
CPC分类号： H03K19/1776
摘要： A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
摘要翻译：可编程逻辑器件（PLD）包括第一存储器块和至少第二存储器块，其中两个存储器块具有不同的存储器大小。

10. 发明申请

US20120072489A1 MOBILE BUSINESS CLIENT 有权
标题翻译：移动业务客户端
公开(公告)号：US20120072489A1
公开(公告)日：2012-03-22
申请号：US13306197
申请日：2011-11-29
申请人： Srinivas Reddy , Juergen Hagedorn , Martin Botschek
发明人： Srinivas Reddy , Juergen Hagedorn , Martin Botschek
IPC分类号： G06F15/16
CPC分类号： G10L13/00
摘要： The subject mater herein relates to computer software and client-server based applications and, more particularly, to a mobile business client. Some embodiments include one or more device-agnostic application interaction models and one or more device specific transformation services. Some such embodiments provide one or more of systems, methods, and software embodied at least in part in a device specific transformation service to transform channel agnostic application interaction models to and from device or device surrogate specific formats.
摘要翻译：本文的主题涉及计算机软件和基于客户机 - 服务器的应用，更具体地涉及移动商务客户端。一些实施例包括一个或多个设备不可知应用交互模型以及一个或多个设备特定转换服务。一些这样的实施例提供至少部分地体现在设备特定转换服务中的系统，方法和软件中的一个或多个，以将信道不可知应用交互模型转换到设备或设备替代特定格式。

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