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1. 发明申请

US20190138274A1 Floating-point number operation circuit and method 审中-公开
公开(公告)号：US20190138274A1
公开(公告)日：2019-05-09
申请号：US16167603
申请日：2018-10-23
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHIA-I CHEN
IPC分类号： G06F7/544 , G06F7/485 , G06F7/487
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/485 , G06F7/487 , G06F7/49947 , G06F2207/3884
摘要： This invention discloses a floating-point number operation circuit and a method thereof. The floating-point number operation circuit is configured to perform a fused multiplication and accumulation (fused mac) operation or a multiplication and accumulation (mac) operation on a first operand, a second operand, and a third operand, or perform a multiplication operation on the first operand and the second operand. The floating-point number operation circuit includes two rounding circuits, a multiplication circuit, a selection circuit, a control circuit, and an addition circuit. The control circuit controls the scheduling of various operations and the use of resources on each calculation path to simplify the circuit and improve the performance of the processor.

2. 发明申请

US20180373536A1 APPARATUSES FOR INTEGRATING ARITHMETIC WITH LOGIC OPERATIONS 审中-公开
公开(公告)号：US20180373536A1
公开(公告)日：2018-12-27
申请号：US15685332
申请日：2017-08-24
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Huaisheng ZHANG , Dacheng LIANG , Boming CHEN , Renyu BIAN
IPC分类号： G06F9/30 , G06F15/16
CPC分类号： G06F9/30014 , G06F7/026 , G06F7/483 , G06F7/49936 , G06F7/57 , G06F7/74 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30134 , G06F9/30185 , G06F9/30189 , G06F9/3887 , G06F9/3893 , G06F15/16 , G06F2207/382 , G06F2207/3824 , H04N19/85
摘要： An apparatus for integrating arithmetic with logic operations contains at least a calculation device and a post-logic unit. The calculation device calculates source data to generate and output first destination data. The post-logic unit, coupled to the calculation device, performs a comparison operation for comparing the first destination data with 0 and outputs a comparison result.

3. 发明申请

US20180373496A1 SELECTIVE UPDATING OF FLOATING POINT CONTROLS 审中-公开
公开(公告)号：US20180373496A1
公开(公告)日：2018-12-27
申请号：US15631061
申请日：2017-06-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/483 , H03M7/24 , G06F9/30
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30076 , G06F9/30087 , G06F9/30101 , G06F9/30189 , G06F9/3836 , H03M7/24
摘要： Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.

4. 发明申请

US20180359084A1 HOMOMORPHIC FACTORIZATION ENCRYPTION 审中-公开
公开(公告)号：US20180359084A1
公开(公告)日：2018-12-13
申请号：US15620034
申请日：2017-06-12
申请人： Microsoft Technology Licensing, LLC
发明人： Prateek Jain , Ramarathnam Venkatesan , Jonathan Lee , Kartik Gupta
IPC分类号： H04L9/08
CPC分类号： H04L9/08 , G06F7/483 , G06F21/602 , G06F2207/4824 , G06N20/00 , H04L9/008 , H04L9/0816 , H04L9/0838 , H04L9/0894
摘要： Systems, methods, and computer-executable instructions for secure data analysis using encrypted data. An encryption key and a decryption key are created. The security of encryption using the encryption key and the decryption key are based upon factoring. A computation key is created based upon the encryption key. Data is encrypted using the encryption key. The encrypted data and the computation key are provided to a remote system. The remote system is requested to perform data analysis on the encrypted data. An encrypted result of the data analysis is received from the remote system. The encrypted result of the data analysis is decrypted with the decryption key.

5. 发明申请

US20180315399A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 审中-公开
公开(公告)号：US20180315399A1
公开(公告)日：2018-11-01
申请号：US15819152
申请日：2017-11-21
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G09G5/36 , G06T1/20 , G09G5/393 , G06N99/00 , G06T15/00
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F2207/3824 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N20/00 , G06T15/005 , G09G5/393
摘要： One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

6. 发明申请

US20180315398A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 审中-公开
公开(公告)号：US20180315398A1
公开(公告)日：2018-11-01
申请号：US15787129
申请日：2017-10-18
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G09G5/36 , G06T1/20 , G09G5/393
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F2207/3824 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N20/00 , G06T15/005 , G09G5/393
摘要： One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

7. 发明授权

US10083008B2 Reproducible stochastic rounding for out of order processors 有权
公开(公告)号：US10083008B2
公开(公告)日：2018-09-25
申请号：US15821171
申请日：2017-11-22
申请人： International Business Machines Corporation
发明人： Jonathan D. Bradbury , Steven R. Carlough , Brian R. Prasky , Eric M. Schwarz
IPC分类号： G06F7/483 , G06F7/58 , G06F17/18 , G06F7/499
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49947 , G06F7/58 , G06F17/18 , G06F2207/483 , G06F2207/58
摘要： A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method d further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

8. 发明申请

US20180225093A1 IMPLEMENTING LOGARITHMIC AND ANTILOGARITHMIC OPERATIONS BASED ON PIECEWISE LINEAR APPROXIMATION 审中-公开
公开(公告)号：US20180225093A1
公开(公告)日：2018-08-09
申请号：US15424063
申请日：2017-02-03
申请人： Intel Corporation
发明人： Kamlesh R. Pillai , Gurpreet S. Kalsi
IPC分类号： G06F7/483 , G06F7/523 , G06F7/556 , H03M7/24 , G06F7/499 , G06F1/03 , G06F7/552
CPC分类号： G06F7/4833 , G06F1/0307 , G06F7/483 , G06F7/49915 , G06F7/5235 , G06F7/5525 , G06F7/556 , G06F2207/3884 , H03M7/24 , H03M7/3064
摘要： Implementations of the disclosure provide logarithm and anti-logarithm operations on a hardware processor based on linear piecewise approximation. An example processor includes a piece wise linear log approximation circuit that receives an input of a floating-point number comprising a sign, an exponent and a mantissa. The piece wise linear log approximation circuit approximates a fractional portion of a fixed point number using a linear approximation of the mantissa of the floating-point number. The piece wise linear log approximation circuit also derives an integer from the exponent.

9. 发明授权

US10037307B2 Device for average calculating of non-linear data 有权
公开(公告)号：US10037307B2
公开(公告)日：2018-07-31
申请号：US15561628
申请日：2016-02-26
申请人： Seokjin Han
发明人： Seokjin Han
IPC分类号： G06F7/38 , G06F17/18 , G06F7/02 , G06F7/24 , G06F7/483 , G06F7/544
CPC分类号： G06F17/18 , G06F7/02 , G06F7/24 , G06F7/483 , G06F7/544 , G06F17/00
摘要： A device for calculating an average of nonlinear data includes: an input module for receiving a nonlinear function F and nonlinear data y1and y2; a comparison module for deriving nonlinear data c1 and c2 sorted in a descending order, by comparing the nonlinear data y1 and y2; an index module for deriving an index value d1 according to a preset computation, from the sorted nonlinear data c1 and c2; a lookup table (LUT) memory for pre-storing an LUT of the index value d1 and a variable B by using a preset computation formula, and deriving the variable B corresponding to the index value d1 if the index value d1 is received; and a computation module for receiving c1 of the sorted nonlinear data and the variable B and deriving a final nonlinear output value A through the preset computation.

10. 发明授权

US10019232B2 Apparatus and method for inhibiting roundoff error in a floating point argument reduction operation 有权
公开(公告)号：US10019232B2
公开(公告)日：2018-07-10
申请号：US15140739
申请日：2016-04-28
申请人： ARM LIMITED
发明人： Jørn Nystad
IPC分类号： G06F7/483 , G06F7/499
CPC分类号： G06F7/49915 , G06F7/483
摘要： An apparatus and method are provided for inhibiting roundoff error in a floating point argument reduction operation. The apparatus has reciprocal estimation circuitry that is responsive to a first floating point value to determine a second floating point value that is an estimated reciprocal of the first floating point value. During this determination, the second floating point value has both its magnitude and its error bound constrained in dependence on a specified value N. Argument reduction circuitry then performs an argument reduction operation using the first and second floating point values as inputs, in order to generate a third floating point value. The use of the specified value N to constrain both the magnitude and the error bound of the second floating point value causes roundoff error to be inhibited in the third floating point value that is generated by the argument reduction operation. This enables such an argument reduction operation to be used as part of a more complex computation, such as a logarithm computation, with the inhibiting of roundoff error in the argument reduction result allowing the overall result to exhibit small relative error across the whole representable input range.

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