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31. 发明申请

US20100022523A1 3-AMINOBENZAMIDE COMPOUNDS AND VANILLOID RECEPTOR SUBTYPE 1 (VR1) INHIBITORS 审中-公开
标题翻译： 3-氨基苯甲酸化合物和VANILLOID受体亚型1（VR1）抑制剂
公开(公告)号：US20100022523A1
公开(公告)日：2010-01-28
申请号：US12430268
申请日：2009-04-27
申请人： YOSHIHISA KOGA , SHINJI YATA , TAKASHI WATANABE , TAKUYA MATSUO , MASAHIRO SAKATA , WATARU KONDO
发明人： YOSHIHISA KOGA , SHINJI YATA , TAKASHI WATANABE , TAKUYA MATSUO , MASAHIRO SAKATA , WATARU KONDO
IPC分类号： A61K31/538 , C07D213/78 , A61K31/44 , C07D265/36 , C07D265/38
CPC分类号： C07C237/40 , C07D213/74 , C07D213/82 , C07D401/12 , C07D413/04
摘要： The present invention relates to a novel 3-aminobenzamide compound represented by the following formula which effectively inhibits vanilloid receptor subtype 1 (VR1) activity (wherein, for example, R1 is a C1-6 alkyl group which may be substituted, R2 is a hydrogen atom, a C1-6 alkyl group or a C1-6 alkoxy group which may be substituted, R3 is a hydrogen atom or a C1-6 alkyl group, R4 is a C1-6 alkyl group, a C1-6 alkoxy group, or a halo C1-6 alkyl group, m is an integer of 1 to 5 and P is a carbon or hetero ring) or a pharmaceutically acceptable salt thereof. The pharmaceutical composition comprising as active ingredients the 3-aminobenzamide compound or a pharmaceutically acceptable salt thereof is useful for treating diseases involved in VR1 activity such as pain, acute pain, chronic pain, neuropathic pain, rheumatoid arthritis pain, and neuralgia.
摘要翻译：本发明涉及有效抑制香草素受体亚型1（VR1）活性的下式所示的新型3-氨基苯甲酰胺化合物（其中，例如，R 1为可被取代的C 1-6烷基，R 2为氢原子，可以被取代的C 1-6烷基或C 1-6烷氧基，R 3是氢原子或C 1-6烷基，R 4是C 1-6烷基，C 1-6烷氧基或卤代C 1-6烷基，m为1〜5的整数，P为碳或杂环）或其药学上可接受的盐。包含3-氨基苯甲酰胺化合物或其可药用盐作为活性成分的药物组合物可用于治疗涉及VR1活性的疾病，例如疼痛，急性疼痛，慢性疼痛，神经性疼痛，类风湿性关节炎疼痛和神经痛。

32. 发明授权

US07625786B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07625786B2
公开(公告)日：2009-12-01
申请号：US11088888
申请日：2005-03-25
申请人： Naoki Makita , Misako Nakazawa , Hideto Ohnuma , Takuya Matsuo
发明人： Naoki Makita , Misako Nakazawa , Hideto Ohnuma , Takuya Matsuo
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02672 , H01L21/02686 , H01L27/1277 , H01L29/78612 , H01L29/78621
摘要： Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.
摘要翻译：解决了在源极/漏极吸杂方法中关于n沟道TFT的现有技术中的问题。在n沟道TFT中，其源极/漏极区仅包含n型杂质。因此，与源极/漏极区域包含n型杂质和较高浓度的p型杂质的p沟道TFT相比，n沟道晶体管的沟道区域的吸杂效率较差。因此，可以通过在其源极/漏极区域的末端设置包含n型杂质的高效吸气区域和浓度为p型的p型杂质来解决n沟道TFT的吸杂效率差的问题的p型杂质的浓度高于n型杂质浓度。

33. 发明授权

US07202149B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07202149B2
公开(公告)日：2007-04-10
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

34. 发明申请

US20070034874A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070034874A1
公开(公告)日：2007-02-15
申请号：US11584524
申请日：2006-10-23
申请人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
发明人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1259 , H01L29/6675 , H01L29/78621 , H01L29/78648
摘要： A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.
摘要翻译：公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 向这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域之上; 和这些层间绝缘膜的开口部分25b，以便位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 以及在第二层间绝缘膜上的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

35. 发明授权

US07141823B2 Thin film transistor semiconductor device 有权
标题翻译：薄膜晶体管半导体器件
公开(公告)号：US07141823B2
公开(公告)日：2006-11-28
申请号：US10254670
申请日：2002-09-26
申请人： Takashi Hamada , Hidekazu Miyairi , Takuya Matsuo , Naoki Makita , Katsumi Nomura
发明人： Takashi Hamada , Hidekazu Miyairi , Takuya Matsuo , Naoki Makita , Katsumi Nomura
IPC分类号： H01L31/072
CPC分类号： H01L29/78696 , H01L27/12 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78627 , H01L29/78675 , H01L2029/7863
摘要： In a TFT with a GOLD structure, there is provided a structure which is able to improve an operating characteristic and reliability and reduce an off current value in order to reduce power consumption of a semiconductor device. The surface of LDD region (4) overlapped with a portion (7a) of a gate electrode through a gate insulating film (6) interposed therebetween is extremely flattened. Thus, it is possible to obtain a TFT structure which is capable of reducing a parasitic capacitance in the LDD region of the TFT with the GOLD structure, reducing an off current value, improving reliability, and enabling high speed operation.
摘要翻译：在具有GOLD结构的TFT中，提供了能够提高工作特性和可靠性并降低截止电流值以降低半导体器件的功耗的结构。通过栅绝缘膜（6）与栅电极的部分（7a）重叠的LDD区（4）的表面极其平坦化。因此，可以获得能够降低具有GOLD结构的TFT的LDD区域中的寄生电容的TFT结构，从而降低截止电流值，提高可靠性并实现高速运行。

36. 发明申请

US20050082537A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050082537A1
公开(公告)日：2005-04-21
申请号：US10963822
申请日：2004-10-14
申请人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
发明人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
IPC分类号： G02F1/1343 , G02F1/1368 , H01L21/20 , H01L21/28 , H01L21/336 , H01L21/77 , H01L21/86 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/04
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1259 , H01L29/6675 , H01L29/78621 , H01L29/78648
摘要： A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.
摘要翻译：公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 向这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域之上; 和这些层间绝缘膜的开口部分25b，以便位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 以及在第二层间绝缘膜上的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

37. 发明授权

US06777713B2 Irregular semiconductor film, having ridges of convex portion 有权
标题翻译：不规则的半导体膜，具有凸部的凸脊
公开(公告)号：US06777713B2
公开(公告)日：2004-08-17
申请号：US10265634
申请日：2002-10-08
申请人： Hidekazu Miyairi , Aiko Shiga , Katsumi Nomura , Naoki Makita , Takuya Matsuo
发明人： Hidekazu Miyairi , Aiko Shiga , Katsumi Nomura , Naoki Makita , Takuya Matsuo
IPC分类号： H01L2900
CPC分类号： H01L27/12 , G02F1/1362 , H01L21/0237 , H01L21/02488 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L21/02686 , H01L27/1277 , H01L29/66757 , H01L29/78621 , H01L29/78675
摘要： By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3. After removing an oxide film on the surface of the semiconductor film, the semiconductor film surface is leveled by irradiating laser light under an inert gas atmosphere or in a vacuum.
摘要翻译：通过添加对JP 8-78329A中公开的技术的新颖改进，提供了具有改善晶体结构的半导体膜的膜特性的制造方法。此外，还提供了具有优异TFT特性的TFT，例如使用半导体膜作为有源层的场效应迁移率，以及TFT的制造方法。将促进硅结晶的金属元素加入到膜内的非晶结构和氧浓度小于5×10 18 / cm 3的半导体膜中。然后对具有非晶结构的半导体膜进行热处理，形成具有晶体结构的半导体膜。随后，除去表面上的氧化物膜。将氧气引入具有晶体结构的半导体膜，并且进行处理，使得膜内的氧浓度为5×10 18 / cm 3至1×10 21 / cm 3。在去除半导体膜表面上的氧化物膜之后，通过在惰性气体气氛或真空中照射激光来平整半导体膜表面。

38. 发明授权

US06756608B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06756608B2
公开(公告)日：2004-06-29
申请号：US10227549
申请日：2002-08-26
申请人： Kenji Kasahara , Naoki Makita , Takuya Matsuo
发明人： Kenji Kasahara , Naoki Makita , Takuya Matsuo
IPC分类号： H01L2904
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02672 , H01L21/02686 , H01L27/1277 , H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678
摘要： A semiconductor device which has satisfactory characteristics is provided. The semiconductor device includes a TFT manufactured by using a satisfactory crystalline semiconductor film and a circuit manufactured by using the TFT. An n-type impurity element (typically, phosphorous) is added to a gettering region of an n-channel TFT. A p-type impurity element (typically, boron) and a rare gas element (typically, argon) are added to a gettering region of a p-channel TFT. Then, there is performed heat treatment for gettering a catalytic element that remains in a semiconductor film.
摘要翻译：提供了具有令人满意的特性的半导体器件。半导体器件包括通过使用令人满意的晶体半导体膜和通过使用TFT制造的电路制造的TFT。 n型杂质元素（通常为磷）被添加到n沟道TFT的吸杂区域。 p型杂质元素（通常为硼）和稀有气体元素（通常为氩）被添加到p沟道TFT的吸杂区域。然后，进行热处理以吸收留在半导体膜中的催化元素。

39. 发明授权

US06727124B2 Method of manufacturing a TFT using a catalytic element to promote crystallization of a semiconductor film and gettering the catalytic element 失效
标题翻译：使用催化元件制造TFT以促进半导体膜的结晶并吸收催化元素的方法
公开(公告)号：US06727124B2
公开(公告)日：2004-04-27
申请号：US10000238
申请日：2001-11-02
申请人： Setsuo Nakajima , Hideto Ohnuma , Naoki Makita , Takuya Matsuo
发明人： Setsuo Nakajima , Hideto Ohnuma , Naoki Makita , Takuya Matsuo
IPC分类号： H01L2184
CPC分类号： H01L27/1214 , G02F1/13454 , H01L27/124 , H01L27/127 , H01L27/1277 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78675 , H01L2029/7863
摘要： A catalytic element for promoting crystallization of an amorphous silicon film is efficiently gettered to provide a highly reliable TFT, and an electro-optical device using the TFT and a method of manufacturing the electro-optical device are provided. The electro-optical device has an n-channel TFT and a p-channel TFT. A semiconductor layer of the p-channel TFT has a channel forming region (13), a region (11) containing an n-type impurity element and a p-type impurity element, and a region (12) containing only a p-type impurity element. In the p-channel TFT, a wiring line for electrically connecting the TFTs is connected to the region (12) containing only a p-type impurity element. The region containing an n-type impurity element in the p-channel TFT is narrower than a region doped with an n-type impurity element in a semiconductor layer of the n-channel TFT.
摘要翻译：提供了一种用于促进非晶硅膜的结晶的催化元件，以提供高度可靠的TFT，并且提供了使用该TFT的电光器件和制造该电光器件的方法。电光装置具有n沟道TFT和p沟道TFT。 p沟道TFT的半导体层具有沟道形成区域（13），包含n型杂质元素和p型杂质元素的区域（11）和仅包含p型杂质元素的区域（12）杂质元素。在p沟道TFT中，用于电连接TFT的布线与仅包含p型杂质元素的区域（12）连接。在p沟道TFT中含有n型杂质元素的区域比n沟道TFT的半导体层中掺杂有n型杂质元素的区域窄。

40. 发明授权

US06271062B1 Thin film semiconductor device including a semiconductor film with high field-effect mobility 失效
标题翻译：薄膜半导体器件包括具有高场效应迁移率的半导体膜
公开(公告)号：US06271062B1
公开(公告)日：2001-08-07
申请号：US09092509
申请日：1998-06-05
申请人： Yukihiko Nakata , Masaki Fujihara , Masahiro Date , Takuya Matsuo , Michiteru Ayukawa , Takashi Itoga
发明人： Yukihiko Nakata , Masaki Fujihara , Masahiro Date , Takuya Matsuo , Michiteru Ayukawa , Takashi Itoga
IPC分类号： H01L2100
CPC分类号： H01L29/4908 , H01L21/02422 , H01L21/02491 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/32055 , H01L29/458 , H01L29/78633 , H01L29/78672 , H01L29/78675 , H01L29/78678
摘要： A thin film transistor includes: a substrate; a gate electrode, a source electrode and a drain electrode formed above the substrate; and an insulating film and a semiconductor film formed between the gate electrode, and the source electrode and the drain electrode, wherein the semiconductor film includes an i-type silicon film, and a portion of the semiconductor film within 50 nm from the insulating film has a microcrystalline structure having a conductivity of 5×10−10 S/cm or more.
摘要翻译：薄膜晶体管包括：基板; 形成在基板上的栅电极，源电极和漏电极; 以及形成在所述栅电极与所述源电极与所述漏电极之间的绝缘膜和半导体膜，其中，所述半导体膜包括i型硅膜，所述半导体膜的距绝缘膜50nm以内的部分具有导电率为5×10 -10 S / cm以上的微晶结构。

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