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31. 发明授权

US07289360B2 Multi-state memory 有权
公开(公告)号：US07289360B2
公开(公告)日：2007-10-30
申请号：US11330923
申请日：2006-01-11
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

32. 发明授权

US07170793B2 Programming inhibit for non-volatile memory 有权
标题翻译：对非易失性存储器进行编程禁止
公开(公告)号：US07170793B2
公开(公告)日：2007-01-30
申请号：US10823421
申请日：2004-04-13
申请人： Daniel C. Guterman
发明人： Daniel C. Guterman
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, the storage elements of a NAND string are partitioned into at least two regions. A first boosting voltage is applied to the first region of the string while a second larger boosting voltage is applied to the second region. The first region includes the addressed row or selected word line for programming. The boosting voltages are applied to the NAND strings of a block while the NAND strings are being inhibited from programming. In this manner, the second boosting voltage can be made larger without inducing program disturb on the memory cells receiving the larger boosting voltage. The boosted voltage potentials of the NAND string channels are trapped within the first region by lowering the boosting voltage on one or more bounding rows. The second boosting voltage is then lowered and data is applied to the bit lines of the NAND strings to select the appropriate strings for programming. The trapped voltage potential discharges or remains in the boosted state for programming depending on whether a string is selected for programming or is to remain inhibited from programming.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，NAND串的存储元件被划分成至少两个区域。第一升压电压被施加到串的第一区域，而第二较大升压电压施加到第二区域。第一个区域包括用于编程的寻址行或所选字线。当NAND串被禁止编程时，升压电压被施加到块的NAND串。以这种方式，可以使第二升压电压更大，而不会对接收到较大升压电压的存储单元造成编程干扰。通过降低一个或多个边界行上的升压电压，NAND串通道的升压电压被捕获在第一区域内。然后降低第二升压电压，并将数据施加到NAND串的位线，以选择适当的编程串。被捕获的电压电位放电或保持在升压状态以进行编程，这取决于是否选择一个串来进行编程，或者被禁止编程。

33. 发明授权

US07088621B2 Bitline governed approach for coarse/fine programming 有权
公开(公告)号：US07088621B2
公开(公告)日：2006-08-08
申请号：US11207427
申请日：2005-08-18
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C16/3459
摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

34. 发明授权

US07071060B1 EEPROM with split gate source side infection with sidewall spacers 失效
标题翻译：具有裂缝栅源的EEPROM与侧壁间隔件的感染
公开(公告)号：US07071060B1
公开(公告)日：2006-07-04
申请号：US09386170
申请日：1999-08-31
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L29/7881
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

35. 发明授权

US06893268B1 Removable mother/daughter peripheral card 失效
公开(公告)号：US06893268B1
公开(公告)日：2005-05-17
申请号：US10841370
申请日：2004-05-06
申请人： Eliyahou Harari , Daniel C. Guterman , Robert F. Wallace
发明人： Eliyahou Harari , Daniel C. Guterman , Robert F. Wallace
IPC分类号： G06F3/00 , G06F12/00 , G06F13/40 , H05K5/02 , H01R29/00 , G06F1/16 , G06F13/12
CPC分类号： G06F13/4068 , G06K19/07741 , H05K5/0265 , H05K5/0282
摘要： A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

36. 发明授权

US06751766B2 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data 有权
标题翻译：通过使用有关存储数据质量的信息，提高纠错码的有效性和操作多级存储器系统
公开(公告)号：US06751766B2
公开(公告)日：2004-06-15
申请号：US10152137
申请日：2002-05-20
申请人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
IPC分类号： G11C2900
CPC分类号： G11C16/3418 , G06F11/1012 , G06F11/1072 , G11C11/56 , G11C11/5621 , G11C16/3431 , G11C29/00 , G11C29/42 , G11C29/76 , G11C2029/0411
摘要： The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the quality indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.
摘要翻译：通过不同的方法评估存储在存储器系统中的数据的质量，并且根据评估的质量操作存储器系统。在读取操作期间可以评估数据质量。随后使用纠错码可以利用质量指示来提高检测和重建数据的效率。或者，可以构建数据质量的统计，并且可以以修改的方式将数字数据值相关联以防止数据损坏。在这两种情况下，根据适当选择的时间表，纠正措施可以针对质量差的数据进行具体实施，并且由于质量指示提供的知识而提高了效率。这些方法对于由多级存储单元构成的高密度存储器系统尤其有用。

37. 发明授权

US06532172B2 Steering gate and bit line segmentation in non-volatile memories 有权
标题翻译：非易失性存储器中的转向门和位线分割
公开(公告)号：US06532172B2
公开(公告)日：2003-03-11
申请号：US09871333
申请日：2001-05-31
申请人： Eliyahou Harari , George Samachisa , Daniel C. Guterman , Jack H. Yuan
发明人： Eliyahou Harari , George Samachisa , Daniel C. Guterman , Jack H. Yuan
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C7/12 , G11C16/0433 , G11C16/0458 , G11C16/0491
摘要： Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.
摘要翻译：转向和位线（例如，闪存EEPROM系统）沿着存储单元阵列的列进行分段。在一个实施例中，其一个段的转向和位线一次连接到相应的全局转向和位线。包括在各个转向门段中的存储单元的行数是单个位线段中包括的行数的倍数，以便具有较少的转向门段。这通过减少转向门所需的段选择晶体管的数量来节省相当大的电路面积，因为这些晶体管必须大于用于选择位线段以用于处理较高电压的晶体管。在另一个实施例中，组合本地导向门线段以便减少它们的数量，然后每个段的减少的数量直接与地址解码器相连，而不需要在解码器之外的多个大的开关晶体管来选择该段。

38. 发明授权

US06266278B1 Dual floating gate EEPROM cell array with steering gates shared adjacent cells 有权
标题翻译：具有转向门的双浮栅EEPROM单元阵列共享相邻单元
公开(公告)号：US06266278B1
公开(公告)日：2001-07-24
申请号：US09634694
申请日：2000-08-08
申请人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
发明人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115
摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.
摘要翻译：具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。双门单元增加了可以存储的数据的密度。不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。因此，转向门由不同但相邻的存储单元的两个浮动门共享。在一个阵列实施例中，浮动栅极形成在基板的表面上，其中增加的转向门的宽度使得它们更容易形成，作为对阵列的缩小的限制，将它们移除，因为它们的尺寸较小，因此需要更少的沿着它们的长度的电触点，因为增加电导，更容易接触，并减少与它们连接所需的导电迹线的数量。在将浮动栅极擦除到选择栅极而不是衬底的阵列中，较宽的转向栅极有利地使其从选择栅极覆盖的扩散分离。单个转向门用于两个浮动栅极的这种使用也允许浮动栅极在另一个实施例中形成在衬底中的沟槽的侧壁上，其间具有公共转向栅极，以进一步增加数据的密度存储。多个数据位也可以存储在每个浮动门上。

39. 发明授权

US5847996A Eeprom with split gate source side injection 失效
标题翻译： Eeprom采用分闸门源注入
公开(公告)号：US5847996A
公开(公告)日：1998-12-08
申请号：US639128
申请日：1996-04-26
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

40. 发明授权

US5798968A Plane decode/virtual sector architecture 失效
公开(公告)号：US5798968A
公开(公告)日：1998-08-25
申请号：US719179
申请日：1996-09-24
申请人： Douglas J. Lee , Sanjay Mehrotra , Mehrdad Mofidi , Daniel C. Guterman
发明人： Douglas J. Lee , Sanjay Mehrotra , Mehrdad Mofidi , Daniel C. Guterman
IPC分类号： G11C5/02 , G11C16/16 , H01L27/115 , G11C16/04
CPC分类号： G11C16/16 , G11C5/025 , H01L27/115
摘要： An EEPROM device having a plurality of flash EEPROM cells organized in right and left half memory planes each having right and left quad memory blocks is described along with corresponding control circuitry including erase circuitry for concurrently erasing selected addressable data sectors of the EEPROM device. Included in the erase circuitry are a plurality of erase voltage generating circuits, a corresponding plurality of switching circuitry, and switch control circuitry shared by the plurality of switching circuitry for controlling the selectable coupling of erase voltages generated by the erase voltage generating circuits to corresponding data sectors of the EEPROM device. To minimize the die size of an integrated circuit including such an EEPROM device, the switching circuitry is formed adjacent elongated gap regions containing contacts for connecting buried diffusion regions of the plurality of flash EEPROM cells to parallel running metal lines to reduce the effective resistance of the bit lines comprising the buried diffusion regions.

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