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1. 发明授权

US09640252B1 Method of operating flash memory unit 有权
公开(公告)号：US09640252B1
公开(公告)日：2017-05-02
申请号：US15226508
申请日：2016-08-02
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang
IPC分类号： G11C16/04 , G11C11/56 , G11C16/26 , G11C16/12 , H01L27/11521
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/0458 , G11C16/10 , G11C16/12 , G11C16/26 , G11C2211/5611 , G11C2211/5612 , G11C2211/5613 , H01L27/11521
摘要： Method of operating flash memory unit is provided. Flash memory unit includes first and second split-gate flash memory units, source and drain of first split-gate flash memory unit are connected with first and third bit lines respectively, source and drain of second split-gate flash memory unit is connected with second and third bit line respectively, first control gates of two split-gate flash memory units are connected with first control gate line, second control gates of two split-gate flash memory units are connected with second control gate line, word line gates of two split-gate flash memory units are connected with word line, method includes configuring voltages to first and third bit lines, word line, first and second control gate lines to select first storage bit in first split-gate flash memory unit and make first storage bit in to-be-read or to-be-programmed state; suspending second bit line; reading or programming first storage bit.

2. 发明授权

US08853765B2 Dense arrays and charge storage devices 有权
公开(公告)号：US08853765B2
公开(公告)日：2014-10-07
申请号：US14227644
申请日：2014-03-27
申请人： SanDisk 3D LLC
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Igor G. Kouznetsov , Mark G. Johnson , Paul Michael Farmwald
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

3. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

4. 发明授权

US07129538B2 Dense arrays and charge storage devices 有权
公开(公告)号：US07129538B2
公开(公告)日：2006-10-31
申请号：US10842008
申请日：2004-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

5. 发明申请

US20040206996A1 Dense arrays and charge storage devices 有权
标题翻译：密集阵列和电荷存储设备
公开(公告)号：US20040206996A1
公开(公告)日：2004-10-21
申请号：US10842008
申请日：2004-05-10
申请人： Matrix Semiconductor, Inc.
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L021/8242
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

6. 发明申请

US20040013001A1 Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell 失效
标题翻译：闪存单元及其制造方法和闪存单元的编程/擦除/读取方法
公开(公告)号：US20040013001A1
公开(公告)日：2004-01-22
申请号：US10616720
申请日：2003-07-10
发明人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
IPC分类号： G11C011/34
CPC分类号： H01L27/11521 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115 , H01L29/7887
摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.
摘要翻译：公开了一种闪存单元及其制造方法及其编程/擦除/读取方法。闪速存储单元包括形成在半导体衬底的给定区域的第一隧道氧化物膜，形成在第一隧道氧化物膜上的第一浮栅，形成在半导体衬底上并沿着第一浮置区的一个侧壁的第二隧道氧化膜栅极，与第一沟槽氧化膜接触时与第一浮栅隔离的第二浮栅;形成在第一浮栅和第二浮栅上的电介质膜，形成在电介质膜上的控制栅，位于第二隧道氧化膜的一侧以下的半导体衬底，以及形成在第一隧道氧化膜的一侧以下的半导体衬底中的第二结区。因此，本发明可以使用现有的工艺技术来实现高密度的2比特单元或3比特单元。此外，鉴于电荷存储/保持以及编程时间，它可以降低制造成本并实现比传统闪存单元有利的高集成闪存单元。

7. 发明申请

US20030002335A1 Nonvolatile memory, cell array thereof, and method for sensing data therefrom 失效
公开(公告)号：US20030002335A1
公开(公告)日：2003-01-02
申请号：US10126584
申请日：2002-04-22
申请人： Hyundai Electronics Industries Co., Ltd.
发明人： Wook Hyun Kwon
IPC分类号： G11C011/34
CPC分类号： H01L29/7887 , G11C11/5621 , G11C11/5642 , G11C16/0458 , G11C16/26 , G11C2211/5612 , H01L27/115
摘要： Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

8. 发明授权

US06501680B1 Nonvolatile memory, cell array thereof, and method for sensing data therefrom 失效
标题翻译：非易失性存储器，其单元阵列，以及用于检测数据的方法
公开(公告)号：US06501680B1
公开(公告)日：2002-12-31
申请号：US10126584
申请日：2002-04-22
申请人： Wook Hyun Kwon
发明人： Wook Hyun Kwon
IPC分类号： G11C700
CPC分类号： H01L29/7887 , G11C11/5621 , G11C11/5642 , G11C16/0458 , G11C16/26 , G11C2211/5612 , H01L27/115
摘要： Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.
摘要翻译：非易失性存储器，其单元阵列以及用于检测数据的方法，所述方法包括以下步骤：选择具有第一浮置栅极和第二浮置栅极，第一控制栅极和第二控制栅极的闪存单元，以及排水和来源; 使电流流过第一浮动栅极下方的第一通道，并检测通过第二浮栅下方的第二通道的电流，从而感测第二浮栅的彩色状态; 使电流流过第二通道并在第一浮栅上导通电平写入，从而形成不同的阈值电压; 测量第一浮动栅下的第一通道的单元电流; 将所测量的电池电流与参考电流进行比较，从而检测第一浮动栅极的电平状态; 以及根据第二浮动栅极的颜色状态和第一浮动栅极的电平状态来感测存储在闪存单元中的信息位。

9. 发明授权

US06266278B1 Dual floating gate EEPROM cell array with steering gates shared adjacent cells 有权
标题翻译：具有转向门的双浮栅EEPROM单元阵列共享相邻单元
公开(公告)号：US06266278B1
公开(公告)日：2001-07-24
申请号：US09634694
申请日：2000-08-08
申请人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
发明人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115
摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.
摘要翻译：具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。双门单元增加了可以存储的数据的密度。不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。因此，转向门由不同但相邻的存储单元的两个浮动门共享。在一个阵列实施例中，浮动栅极形成在基板的表面上，其中增加的转向门的宽度使得它们更容易形成，作为对阵列的缩小的限制，将它们移除，因为它们的尺寸较小，因此需要更少的沿着它们的长度的电触点，因为增加电导，更容易接触，并减少与它们连接所需的导电迹线的数量。在将浮动栅极擦除到选择栅极而不是衬底的阵列中，较宽的转向栅极有利地使其从选择栅极覆盖的扩散分离。单个转向门用于两个浮动栅极的这种使用也允许浮动栅极在另一个实施例中形成在衬底中的沟槽的侧壁上，其间具有公共转向栅极，以进一步增加数据的密度存储。多个数据位也可以存储在每个浮动门上。

10. 发明授权

US06243289B1 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation 失效
标题翻译：双浮栅可编程只读存储单元结构及其制造和操作方法
公开(公告)号：US06243289B1
公开(公告)日：2001-06-05
申请号：US09056764
申请日：1998-04-08
申请人： Fernando Gonzalez , Francis L. Benistant
发明人： Fernando Gonzalez , Francis L. Benistant
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L29/66825 , H01L29/7887
摘要： A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.
摘要翻译：公开了能够存储多位二进制数据的晶体管形式的闪存单元。一对浮动门设置在控制门下方。控制栅极连接到字线，而源极和漏极区域连接到相应的数字线。浮动栅极通过控制施加到字线和数字线的电压而被单独充电和读出。读出的电荷被解码为多位二进制值。还公开了制造存储器单元并进行操作的方法。

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