专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20140367778A1 LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR (LDMOS) 有权
标题翻译：侧向扩散金属氧化物半导体（LDMOS）
公开(公告)号：US20140367778A1
公开(公告)日：2014-12-18
申请号：US13920236
申请日：2013-06-18
申请人： International Business Machines Corporation
发明人： Santosh Sharma , Yun Shi , Anthony K. Stamper
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/404 , H01L29/66681
摘要： A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.
摘要翻译：横向扩散金属氧化物半导体（LDMOS）包括在衬底的顶表面中具有STI结构的半导体衬底，STI结构下方的漂移区域，以及STI结构的相对侧上的源极区域和漏极区域。栅极导体在STI结构和源极区之间的间隙上在衬底上，并且部分地与漂移区重叠。保形介质层位于顶表面上，并在栅极导体上形成台面。保形介电层具有嵌入其中的保形蚀刻停止层。接触柱延伸穿过介电层和蚀刻停止层，并连接到源极区，漏极区和栅极导体。源电极接触源极接触柱，栅电极接触栅接触柱，而漏电极接触漏接触柱。漂移电极在漂移区域之上。

32. 发明申请

US20140225231A1 MODULATING BOW OF THIN WAFERS 审中-公开
标题翻译：微波调制波
公开(公告)号：US20140225231A1
公开(公告)日：2014-08-14
申请号：US13764852
申请日：2013-02-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey P. Gambino , John C. Hall , Kenneth F. McAvey, JR. , Charles F. Musante , Anthony K. Stamper
IPC分类号： H01L23/00 , H01L21/02
CPC分类号： H01L23/562 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material. The wafer has a front side and a back side. A cross-section of the wafer is reduced by thinning material from the front side of the wafer. A plurality of circuits comprising individual semiconductor devices are formed on the front side of the wafer. A stress-balancing layer is formed on the back side of the wafer. The stress-balancing layer comprises at least one of a polymer film and/or a metal film having at least one metal layer. A heat treatment is applied to the wafer. The heat treatment may be an annealing process to a temperature between 150° C. and 450° C., which develops an in-situ bilateral tensile stress in the stress-balancing layer that modulates the bowing of thin wafers.
摘要翻译：装置和方法调节薄晶片的弯曲。根据一种方法，晶片由半导体材料形成。晶片具有前侧和后侧。通过从晶片的前侧减薄材料来减小晶片的横截面。包括单个半导体器件的多个电路形成在晶片的前侧。应力平衡层形成在晶片的背面。应力平衡层包括具有至少一个金属层的聚合物膜和/或金属膜中的至少一种。对晶片进行热处理。热处理可以是在150℃和450℃之间的温度的退火过程，其在应力平衡层中产生原位双边拉伸应力，其调节薄晶片的弯曲。

33. 发明申请

US20140097434A1 BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS 有权
标题翻译：后端金属氧化物半导体变送器
公开(公告)号：US20140097434A1
公开(公告)日：2014-04-10
申请号：US13644918
申请日：2012-10-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/775 , G06F17/50 , H01L21/336
CPC分类号： H01L29/93 , H01L27/0688 , H01L27/0808
摘要： Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.
摘要翻译：变容二极管的器件结构，设计结构和制造方法。器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。半导体本体由非晶态或多晶态的含硅半导体材料构成。器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

34. 发明申请

US20130161283A1 SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING 审中-公开
公开(公告)号：US20130161283A1
公开(公告)日：2013-06-27
申请号：US13775338
申请日：2013-02-25
申请人： International Business Machines Corporation
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H01L41/33 , H01L41/332
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.

35. 发明申请

US20130147015A1 DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING 有权
标题翻译：深层剥离电容器及其形成方法
公开(公告)号：US20130147015A1
公开(公告)日：2013-06-13
申请号：US13765105
申请日：2013-02-12
申请人： International Business Machines Corporation
发明人： James S. Nakos , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01L29/66181 , H01L29/945
摘要： Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.
摘要翻译：公开了用于形成硅化深沟槽去耦电容器的解决方案。一方面，一种形成半导体器件的方法包括：在硅衬底中形成外部沟槽，所述硅衬底的所述成形暴露部分位于所述硅衬底的上表面下方; 在沟槽内沉积介电衬垫层; 在所述介质衬底层上沉积掺杂多晶硅层，所述掺杂多晶硅层在所述硅衬底中形成内部沟槽; 在所述掺杂多晶硅层的一部分上形成硅化物层; 在所述内沟槽内形成中间接触层; 以及在所述中间接触层的一部分和所述硅化物层的一部分上形成接触。

36. 发明授权

US11167980B2 Micro-electro-mechanical system (MEMS) structures and design structures 有权
公开(公告)号：US11167980B2
公开(公告)日：2021-11-09
申请号：US14837024
申请日：2015-08-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael T. Brigham , Christopher V. Jahnes , Cameron E. Luce , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , Eric J. White
IPC分类号： B81C1/00 , B81B3/00 , G06F30/20
摘要： Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

37. 发明授权

US11111138B2 Planar cavity mems and related structures, methods of manufacture and design structures 有权
公开(公告)号：US11111138B2
公开(公告)日：2021-09-07
申请号：US16579983
申请日：2019-09-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anthony K. Stamper , John G. Twombly
IPC分类号： B81C1/00 , H01L41/113 , H01H1/00 , H01H57/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

38. 发明授权

US10745273B2 Method of manufacturing a switch 有权
公开(公告)号：US10745273B2
公开(公告)日：2020-08-18
申请号：US15627673
申请日：2017-06-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01H11/00 , H01H65/00 , B81C1/00 , H01H59/00 , H01H49/00 , H01H1/00 , H01H1/58 , H01H50/00
摘要： MEMS switches and methods of manufacturing MEMS switches is provided. The MEMS switch having at least two cantilevered electrodes having ends which overlap and which are structured and operable to contact one another upon an application of a voltage by at least one fixed electrode.

39. 发明授权

US10584026B2 Planar cavity MEMS and related structures, methods of manufacture and design structures 有权
公开(公告)号：US10584026B2
公开(公告)日：2020-03-10
申请号：US15973958
申请日：2018-05-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Christopher V. Jahnes , Anthony K. Stamper
IPC分类号： H01P1/10 , B81B3/00 , H01L41/113 , B81C1/00 , H01H57/00 , G06F17/50 , H01H1/00 , H01H59/00 , B81B1/00
摘要： A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.

40. 发明授权

US10566235B2 Backside contact to a final substrate 有权
公开(公告)号：US10566235B2
公开(公告)日：2020-02-18
申请号：US15788536
申请日：2017-10-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey P. Gambino , Mark D. Jaffe , Steven M. Shank , Anthony K. Stamper
IPC分类号： H01L21/74 , H01L21/768 , H01L23/482 , H01L21/683 , H01L21/762 , H01L23/532 , H01L27/12 , H01L29/06 , H01L29/10
摘要： A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式