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31. 发明授权

US08806402B2 Modeling multi-patterning variability with statistical timing 有权
标题翻译：用统计时序建模多图案变异
公开(公告)号：US08806402B2
公开(公告)日：2014-08-12
申请号：US13665466
申请日：2012-10-31
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/08 , G06F2217/10 , G06F2217/12 , G06F2217/84
摘要： Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.
摘要翻译：描述了在IC制造期间利用统计时序分析建模多图案变化的系统和方法。该方法可以被提供在具有计算机可执行代码的计算机基础结构中，计算机可执行代码有形地体现在具有可编程指令的计算机可读存储介质上，该程序指令可操作以限定集成电路设计中的至少所述编程指令进一步可操作以将集成电路设计的至少一个级别中的至少两个模式的所述至少一个变化源建模为至少两个变异性源。

32. 发明授权

US08769452B2 Parasitic extraction in an integrated circuit with multi-patterning requirements 有权
标题翻译：具有多图案化要求的集成电路中的寄生提取
公开(公告)号：US08769452B2
公开(公告)日：2014-07-01
申请号：US13665315
申请日：2012-10-31
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/82
摘要： Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.
摘要翻译：提供了用于在具有多图案化要求的集成电路的设计中提取寄生效应的系统和方法。该方法包括确定电阻解和电容解。该方法还包括执行电阻解和电容解的寄生提取以产生电阻解和电容解的平均值。该方法还包括在寄生提取期间捕获每个电阻解决方案和电容解的多图案变化源。该方法还包括确定每个捕获的变化源与相应的参数矢量的灵敏度。该方法还包括通过将每个电阻解和电容解乘以每个相应捕获的变化源的灵敏度来确定统计寄生效应。该方法还包括以矢量形式和折叠缩小矢量形式中的至少一个生成统计寄生效应作为输出。

33. 发明申请

US20130159953A1 PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS 有权
标题翻译：执行具有不可分割统计和确定变化的统计时序分析
公开(公告)号：US20130159953A1
公开(公告)日：2013-06-20
申请号：US13768563
申请日：2013-02-15
申请人： International Business Machines Corporation
发明人： Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.
摘要翻译：在一个实施例中，本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆，其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数，以及第二工艺参数其与第一过程参数是统计的且不可分离的，并且使用定时数量执行单个定时运行，其中单个定时运行产生到达时间，所需的到达时间和定时偏移在输出，锁存器和电路节点集成电路芯片。计算的到达时间，所需的到达时间和定时松弛可以被投影到确定性变化的角落值，以便获得相应角落处的延迟和压摆的统计模型。

34. 发明授权

US10970448B2 Partial parameters and projection thereof included within statistical timing analysis 有权
公开(公告)号：US10970448B2
公开(公告)日：2021-04-06
申请号：US16515177
申请日：2019-07-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Jeffrey G. Hemmett , Lansing D. Pickup , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F30/3312 , G06F119/12
摘要： Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

35. 发明授权

US10489540B2 Integrating manufacturing feedback into integrated circuit structure design 有权
公开(公告)号：US10489540B2
公开(公告)日：2019-11-26
申请号：US15810184
申请日：2017-11-13
申请人： International Business Machines Corporation
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

36. 发明授权

US10394982B2 Partial parameters and projection thereof included within statistical timing analysis 有权
公开(公告)号：US10394982B2
公开(公告)日：2019-08-27
申请号：US14190646
申请日：2014-02-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Jeffrey G. Hemmett , Lansing D. Pickup , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
摘要： Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

37. 发明授权

US10346569B2 Multi-sided variations for creating integrated circuits 有权
公开(公告)号：US10346569B2
公开(公告)日：2019-07-09
申请号：US15851815
申请日：2017-12-22
申请人： International Business Machines Corporation
发明人： Robert J. Allen , Nathan C. Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Debjit Sinha , Natesan Venkateswaran , Vladimir Zolotov
IPC分类号： G06F17/50
摘要： Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

38. 发明授权

US10031985B2 Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit 有权
公开(公告)号：US10031985B2
公开(公告)日：2018-07-24
申请号：US14991039
申请日：2016-01-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathan Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
摘要： Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

39. 发明授权

US10013516B2 Selection of corners and/or margins using statistical static timing analysis of an integrated circuit 有权
公开(公告)号：US10013516B2
公开(公告)日：2018-07-03
申请号：US15332385
申请日：2016-10-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Alexander J. Suess , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F17/5081 , G06F2217/80 , G06F2217/84
摘要： Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

40. 发明申请

US20180096089A1 INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGN 审中-公开
公开(公告)号：US20180096089A1
公开(公告)日：2018-04-05
申请号：US15810184
申请日：2017-11-13
申请人： International Business Machines Corporation
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

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