专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20210174190A1 NEURAL NETWORK TRAINING USING A DATA FLOW GRAPH AND DYNAMIC MEMORY MANAGEMENT 有权
公开(公告)号：US20210174190A1
公开(公告)日：2021-06-10
申请号：US16704240
申请日：2019-12-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Gradus Janssen , Vladimir Zolotov , Tung D. Le
IPC分类号： G06N3/08 , G06N3/04 , G06N3/06 , G06K9/62 , G06F9/50
摘要： Processing a neural network data flow graph having a set of nodes and a set of edges. An insertion point is determined for a memory reduction or memory restoration operation. The determination is based on computing tensor timing slacks (TTS) for a set of input tensors; compiling a candidate list (SI) of input tensors, from the set of input tensors, using input tensors having corresponding TTS values larger than a threshold value (thTTS); filtering the SI to retain input tensors whose size meets a threshold value (thS); and determining an insertion point for the operation using the SI based on the filtering. A new data flow graph is generated or an existing one is modified using this process.

2. 发明授权

US10606970B2 Selection of corners and/or margins using statistical static timing analysis of an integrated circuit 有权
公开(公告)号：US10606970B2
公开(公告)日：2020-03-31
申请号：US15951713
申请日：2018-04-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Alexander J. Suess , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
摘要： Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

3. 发明授权

US10460068B2 Coupling aware wire capacitance adjust at global routing 有权
公开(公告)号：US10460068B2
公开(公告)日：2019-10-29
申请号：US16384004
申请日：2019-04-15
申请人： International Business Machines Corporation
发明人： Ronald D. Rose , Vladimir Zolotov
IPC分类号： G06F17/50
摘要： A system for semiconductor chip fabrication. A host system hosts a capacitance adjust tool for performing calculating a ground capacitance adjust for a wire segment going through routing tiles according to the following operations; providing the routing tiles having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, to guide placement of the wire segment in the routing tiles to avoid coupling noise; and outputting the placement of the wire segments to a tool for manufacturing the semiconductor chip.

4. 发明授权

US10289776B2 Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit 有权
公开(公告)号：US10289776B2
公开(公告)日：2019-05-14
申请号：US15980999
申请日：2018-05-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathan Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
摘要： Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

5. 发明申请

US20180239858A1 MULTI-SIDED VARIATIONS FOR CREATING INTEGRATED CIRCUITS 审中-公开
公开(公告)号：US20180239858A1
公开(公告)日：2018-08-23
申请号：US15436895
申请日：2017-02-20
申请人： International Business Machines Corporation
发明人： Robert J. Allen , Nathan C. Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Debjit Sinha , Natesan Venkateswaran , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/505 , G06F17/5063 , G06F2217/84
摘要： Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

6. 发明授权

US09836434B2 Runtime of CUBLAS matrix multiplication on GPU 有权
公开(公告)号：US09836434B2
公开(公告)日：2017-12-05
申请号：US14823889
申请日：2015-08-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alexey Y. Lvov , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/16 , G06T1/20
CPC分类号： G06F17/16 , G06T1/20 , G06T2200/28
摘要： Methods for improving matrix multiplication runtimes are provided. A method includes determining, by a GPU, optimal partitions for matrix-by-matrix multiplication of two factor matrices having sizes known a priori. The determining step includes performing offline a plurality of matrix-by-matrix multiplication executions, each for a respective different combination of two-way partitions across a plurality of partition sizes. The determining step further includes determining offline a respective performance number for each of the executions based on runtime. The determining step also includes recursively repeating offline said performing and determining steps until the respective performance number ceases to improve for best-performing combinations of the two-way partitions and saving the best performing combinations of the two-way partitions as the optimal partitions. The method further includes performing online, by the GPU, the matrix-by-matrix multiplication of the two factor matrices using calls for a given one of the best performing combinations of the two-way partitions.

7. 发明申请

US20170140090A1 ANALYSIS OF COUPLED NOISE FOR INTEGRATED CIRCUIT DESIGN 审中-公开
公开(公告)号：US20170140090A1
公开(公告)日：2017-05-18
申请号：US14944552
申请日：2015-11-18
申请人： International Business Machines Corporation
发明人： Steven J. Kurtz , Mark A. Lavin , Ronald D. Rose , Richard W. Taggart , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/504 , G06F17/5068 , G06F2217/82
摘要： A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

8. 发明授权

US09189584B2 Cross-talk noise computation using mixed integer linear program problems and their solutions 有权
标题翻译：使用混合整数线性程序问题及其解决方案的串扰噪声计算
公开(公告)号：US09189584B2
公开(公告)日：2015-11-17
申请号：US13970695
申请日：2013-08-20
申请人： International Business Machines Corporation
发明人： Peter Feldmann , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , G06F2217/82
摘要： A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.
摘要翻译：一种方法包括形成捕获至少多个定时窗口的混合整数线性问题（MILP），通过电磁耦合到电路中的受害网络的侵入网络产生潜在地有助于最大值的计算的串扰噪声脉冲受害网的噪音。解决了MILP以确定受害网络的最大噪声。响应于满足一个或多个标准的最大噪声，至少输出受害者网络的指示。形成可以包括使用重叠定时窗口来形成线性问题，噪声脉冲对于噪声脉冲有助于最大噪声，并将线性问题转换为混合整数线性问题，通过引入确定是否重叠或不重叠的线性问题二进制变量来自一个或多个侵略者网络的噪声脉冲有助于最大噪声。还公开了装置和程序产品。

9. 发明申请

US20150046891A1 Cross-Talk Noise Computation Using Mixed Integer Linear Program Problems And Their Solutions 审中-公开
公开(公告)号：US20150046891A1
公开(公告)日：2015-02-12
申请号：US13964312
申请日：2013-08-12
申请人： International Business Machines Corporation
发明人： Peter Feldmann , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , G06F2217/82
摘要： A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.

10. 发明授权

US08850378B2 Hierarchical design of integrated circuits with multi-patterning requirements 有权
标题翻译：具有多图案化要求的集成电路的分层设计
公开(公告)号：US08850378B2
公开(公告)日：2014-09-30
申请号：US13665276
申请日：2012-10-31
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5009 , G06F17/5068 , G06F17/5081
摘要： Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.
摘要翻译：描述了用于避免在具有多图案化要求的集成电路的分层设计中对单元布置的限制的系统和方法。该方法可以在具有计算机可执行代码的计算机可执行代码中实现，该计算机可执行代码有形地体现在具有可编程指令的计算机可读存储介质上，该程序指令可操作以将颜色分配给第一单元中的每个图案形状，为第二单元中的每个图案形状分配颜色，表征第一单元格中每个图案形状的感兴趣量，确定在第一单元格中分配的颜色与第二单元格中分配的颜色可以一一对应，表征第二单元格中每个图案形状的感兴趣量使用针对第一小区表征的兴趣量，并对第一小区和第二小区的兴趣量进行建模。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式