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31. 发明授权

US08564998B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08564998B2
公开(公告)日：2013-10-22
申请号：US13459017
申请日：2012-04-27
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
摘要翻译：内容可寻址存储器中的阵列区域和功耗降低。通常为多个条目提供用于执行匹配确定和大小确定的比较器，每个条目存储要检索的数据。每个条目包括用于存储数据的数据存储单元和用于存储掩码位的掩码单元。掩模单元的数量小于数据存储单元的数量。搜索数据通过搜索数据总线传送到比较器。根据预定规则选择其中一个条目。比较器对掩码位进行解码，产生掩码指令信号，并且在搜索数据和存储在所选条目中的要检索的数据之间进行匹配比较和大小比较。

32. 发明授权

US08284582B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08284582B2
公开(公告)日：2012-10-09
申请号：US13023529
申请日：2011-02-08
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
摘要翻译：本发明旨在减少内容可寻址存储器中的阵列面积和功耗。通常为多个条目提供用于执行匹配确定和大小确定的比较器，每个条目存储要检索的数据。每个条目包括用于存储数据的数据存储单元和用于存储掩码位的掩码单元。掩模单元的数量小于数据存储单元的数量。搜索数据通过搜索数据总线传送到比较器。根据预定规则选择其中一个条目。比较器对掩码位进行解码，产生掩码指令信号，并且在搜索数据和存储在所选条目中的要检索的数据之间进行匹配比较和大小比较。

33. 发明授权

US06868552B1 Ingress noise control system and ingress noise blocking device 失效
标题翻译：入口噪声控制系统和入口噪声抑制装置
公开(公告)号：US06868552B1
公开(公告)日：2005-03-15
申请号：US09589426
申请日：2000-06-07
申请人： Shigefumi Masuda , Hiroo Tamura , Minoru Ishida , Kazunari Inoue , Takayuki Tyou
发明人： Shigefumi Masuda , Hiroo Tamura , Minoru Ishida , Kazunari Inoue , Takayuki Tyou
IPC分类号： H04B3/36 , H04B15/00 , H04N7/10 , H04N21/647 , H04N7/173
CPC分类号： H04N7/102 , H04N7/17309
摘要： The present invention concerns an ingress noise control system and an ingress noise blocking device which are used in a cable system to suppress ingress noise. In the cable system providing two-way communication using different frequency bands for transmission of upstream and downstream signals, the ingress noise control system includes, within a distribution unit, a two-way amplification unit, etc. provided in an upstream signal transmission path, a synchronous detection controller 6 for synchronously detecting the upstream signal transmitted from terminal equipment and separated by a low-pass filter 4 in a second separation filter 2, a gate switch circuit 5 which is turned on by the synchronous detection controller 6 to pass the upstream signal only when the upstream signal is synchronously detected, and an indicator 7 for indicating the on/off state of the gate switch circuit 5.
摘要翻译：本发明涉及一种在电缆系统中用于抑制入射噪声的入口噪声控制系统和入口噪声阻断装置。在提供使用不同频带进行上下行信号传输的双向通信的电缆系统中，进入噪声控制系统在分配单元内包括设置在上游信号传输路径中的双向放大单元等，同步检测控制器6，用于同步检测从终端设备发送并由第二分离滤波器2中的低通滤波器4分离的上行信号;同步检测控制器6，由同步检测控制器6接通以通过上游只有当同步检测到上行信号时才产生信号;以及指示器7，用于指示门开关电路5的开/关状态。

34. 发明授权

US06795325B1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06795325B1
公开(公告)日：2004-09-21
申请号：US10715455
申请日：2003-11-19
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C1500
CPC分类号： G11C11/56 , G11C15/00
摘要： A semiconductor memory can reduce its power consumption by decreasing the activation frequency of search lines during search operation. It includes a CAM cell block for storing memory data expressing each combination of digital values stored in four memory cells in terms of a 2-bit digital value; search lines on which a digital value to be matched with a digital value stored in the memory cells is placed; a search data setting section for placing individual 1-bit digital values on the search lines connected to the memory cells to set the search data expressing a 4-bit combination of digital values in terms of the 2-bit digital value; transistors for deciding match/mismatch between the memory data and search data; and the match line 3 for outputting the decision result.
摘要翻译：半导体存储器可以通过在搜索操作期间降低搜索线的激活频率来降低其功耗。它包括CAM单元块，用于存储表示以2位数字值表示存储在四个存储器单元中的数字值的每个组合的存储器数据; 搜索与存储在存储单元中的数字值匹配的数字值的搜索行; 搜索数据设置部分，用于在连接到存储器单元的搜索线上放置单个1位数字值，以设置表示2位数字值的数字值的4位组合的搜索数据; 用于确定存储器数据和搜索数据之间的匹配/不匹配的晶体管; 以及用于输出判定结果的匹配线3。

35. 发明授权

US06731526B2 CAM cell array, TCAM cell, TCAM cell array, address search memory, and network address search apparatus 失效
标题翻译： CAM单元阵列，TCAM单元，TCAM单元阵列，地址搜索存储器和网络地址搜索装置
公开(公告)号：US06731526B2
公开(公告)日：2004-05-04
申请号：US10374103
申请日：2003-02-27
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A content addressable memory (CAM) cell array includes a first-stage memory cell array and a second-stage memory cell array. Only when data on search output lines (match lines) connected to the first-stage memory cell array are coincident, the second-stage memory cell array performs search operation. Therefore, power consumption of the CAM cell array can be reduced.
摘要翻译：内容可寻址存储器（CAM）单元阵列包括第一级存储单元阵列和第二级存储单元阵列。连接到第一级存储单元阵列的搜索输出线（匹配线）上的数据一致时，第二级存储单元阵列执行搜索操作。因此，可以减少CAM单元阵列的功耗。

36. 发明授权

US6043829A Frame buffer memory with look-up table 失效
标题翻译：具有查找表的帧缓冲存储器
公开(公告)号：US6043829A
公开(公告)日：2000-03-28
申请号：US959260
申请日：1997-10-28
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C11/401 , G06T1/60 , G09G5/06 , G09G5/395 , G06F15/76
CPC分类号： G09G5/395 , G09G5/06
摘要： A frame buffer memory includes, on a semiconductor substrate: a DRAM array in which image information including frame information and window information are stored; two serial access memories for serially outputting the image information read from DRAM array by interleave method; a look-up table for outputting a selection signal in accordance with window information input; and a multiplexer for selectively outputting frame information input in accordance with said selection signal.
摘要翻译：帧缓冲存储器包括在半导体衬底上：存储包括帧信息和窗口信息的图像信息的DRAM阵列; 两个串行访问存储器，用于通过交错方法串行输出从DRAM阵列读取的图像信息; 一个用于根据窗口信息输入输出选择信号的查找表; 以及多路复用器，用于选择性地输出根据所述选择信号输入的帧信息。

37. 发明授权

US5229965A Serial accessible semiconductor memory device 失效
标题翻译：串行可访问半导体存储器件
公开(公告)号：US5229965A
公开(公告)日：1993-07-20
申请号：US754897
申请日：1991-09-04
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/409
CPC分类号： G11C7/1093 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087
摘要： The semiconductor memory device includes a serial memory cell array and an input-output circuit. The input-output circuit includes first and second latch circuits, first and second transfer circuits and an output circuit. The first transfer circuit transfers the information read from the serial memory cell array to the first latch circuit. The second transfer circuit transfers the information from the first latch circuit 103 to the second latch circuit 105. The output circuit externally supplies as output the information held in the second latch circuit. A clock generator supplies a clock signal to the first and the second transfer circuits and the output circuit so that the output operation by the output circuit may be effected, and then the transfer operation by the first transfer circuit may be effected after the transfer by the second transfer circuit has been effected.
摘要翻译：半导体存储器件包括串行存储单元阵列和输入 - 输出电路。输入输出电路包括第一和第二锁存电路，第一和第二传输电路和输出电路。第一传输电路将从串行存储单元阵列读取的信息传送到第一锁存电路。第二传送电路将信息从第一锁存电路103传送到第二锁存电路105.输出电路作为输出提供保存在第二锁存电路中的信息。时钟发生器向第一和第二传送电路和输出电路提供时钟信号，使得可以实现输出电路的输出操作，然后第一传送电路的传送操作可以在通过第二传输电路已经实现。

38. 发明授权

US4399390A Built-in starter type fluorescent lamp socket 失效
标题翻译：内置起动器型荧光灯插座
公开(公告)号：US4399390A
公开(公告)日：1983-08-16
申请号：US215769
申请日：1980-12-12
申请人： Hiroshi Oshita , Hiromi Adachi , Kazunari Inoue
发明人： Hiroshi Oshita , Hiromi Adachi , Kazunari Inoue
IPC分类号： H01R33/945 , H01J61/54 , H01R13/66 , H01R33/05 , H01R33/08 , H05B41/04
CPC分类号： H01J61/54 , H01R33/05 , H01R13/66 , Y10S315/05
摘要： A built-in starter type fluorescent lamp socket in which the starter is entirely incorporated with the socket with no protruding parts and in which it is not necessary to replace the starter. The socket includes a socket body, pairs of starter contacts and power source contacts operatively positioned in the socket body for making connection with fluorescent lamp pins, and an electronic starter positioned in the socket body and connected to the starter contacts. The electronic starter includes a non-linear dielectric element and a thyristor coupled in parallel and across the starter contacts. The anode of the thyristor is coupled through a Zener diode to the common connection point between voltage division resistors also coupled across the starter contacts. The socket body may include a casing having lamp pin inserting holes and a cover for covering the rear side of the casing wherein the cover may be shaped in the form of a box in which the electronic starter is mounted. In a preferred embodiment, the casing is provided with a lead wire receiving portion which together with the cover clamp the lead wires which are connected to the power source contacts.
摘要翻译：一种内置的起动器型荧光灯插座，其中起动器与插座完全结合，没有突出部分，并且不需要更换起动器。插座包括插座主体，成对的起动器触点和可操作地定位在插座主体中用于与荧光灯销连接的电源触点，以及定位在插座主体中并连接到起动器触点的电子启动器。电子启动器包括非线性介质元件和并联耦合并跨过起动器触点的晶闸管。晶闸管的阳极通过齐纳二极管耦合到也耦合在起动器触点上的分压电阻之间的公共连接点。插座主体可以包括具有灯销插入孔的壳体和用于覆盖壳体的后侧的盖，其中盖可以以安装有电子起动器的盒的形式成形。在优选实施例中，壳体设置有引线接收部分，其与盖夹持连接到电源触点的引线。

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