专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06834003B2 Content addressable memory with PFET passgate SRAM cells 失效
标题翻译：内置可寻址存储器，具有PFET通道SRAM单元
公开(公告)号：US06834003B2
公开(公告)日：2004-12-21
申请号：US10065842
申请日：2002-11-25
申请人： Fred John Towler , Robert C. Wong
发明人： Fred John Towler , Robert C. Wong
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.
摘要翻译：具有PFET通道SRAM单元的内容寻址存储器（CAM）单元，由于8个PFET器件和8个NFET器件的数量更多，导致更小的单元尺寸。 PFET Passgates允许降低SRAM单元下拉器件的尺寸，并在待机或读/写期间降低SRAM中的功耗。

2. 发明授权

US06785153B2 Tertiary CAM cell 失效
标题翻译：三级CAM单元
公开(公告)号：US06785153B2
公开(公告)日：2004-08-31
申请号：US10684388
申请日：2003-10-15
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： G11C1500
CPC分类号： G11C15/043
摘要： A tertiary CAM cell with three bits of storage, the three bits of storage are arranged to support three stable states which can be read from the CAM cell without requiring a charge restoration operation. The three stables states are those states where one of the three bits is at a first logical state while the remaining two bits are at a second logical state. The three stables states may be used to encode the three logical states used in a ternary CAM.
摘要翻译：具有三位存储的三级CAM单元，三位存储器被布置成支持三种可以从CAM单元读取的稳定状态，而不需要电荷恢复操作。三个状态是这三个位之一处于第一逻辑状态而其余两位处于第二逻辑状态的状态。三个状态可用于对三进制CAM中使用的三种逻辑状态进行编码。

3. 发明授权

US06747886B1 Content addressable memory with shifted enable signal 失效
标题翻译：内容可寻址存储器，具有移位的使能信号
公开(公告)号：US06747886B1
公开(公告)日：2004-06-08
申请号：US10401743
申请日：2003-03-31
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A content addressable memory includes a seek access circuit with four transistors connected in series between a pair of bit lines. The two inner transistors are driven by a data storage circuit; the outer two transistors function as enable transistors. A level shifting circuit receives an enable signal and shifts one or both of the logic levels of the enable signal so as to widen the potential difference between them. The shifted enable signal drives the enable transistors in the seek access circuit. Shifting the high logic level of the enable signal upward speeds up seek access by reducing the on-resistance of the enable transistors. Shifting the low logic level of the enable signal downward reduces subthreshold leakage through the seek access circuit, thereby reducing current consumption, speeding up read and write access, and preventing access errors.
摘要翻译：内容可寻址存储器包括具有串联连接在一对位线之间的四个晶体管的寻道存取电路。两个内部晶体管由数据存储电路驱动; 外部两个晶体管用作启用晶体管。电平移位电路接收使能信号并移位使能信号的逻辑电平中的一个或两者，以便扩大它们之间的电位差。移位的使能信号驱动寻道存取电路中的使能晶体管。通过降低启用晶体管的导通电阻，使启动信号的高逻辑电平向上移动可以加快寻道访问。向下移动使能信号的低逻辑电平可以降低通过寻道存取电路的次阈值泄漏，从而减少电流消耗，加速读写访问，并防止访问错误。

4. 发明授权

US06747885B2 Ternary content addressable memory device 有权
标题翻译：三进制内容可寻址存储设备
公开(公告)号：US06747885B2
公开(公告)日：2004-06-08
申请号：US10303662
申请日：2002-11-25
申请人： Chul-Sung Park
发明人： Chul-Sung Park
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A ternary content addressable memory (TCAM) having an array of cells arranged in rows and columns, each cell comprising of a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement. A compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node. A match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal. A mask memory cell for storing and outputting mask data and a mask circuit coupled to the match circuit and the match input line and the match output line for masking the compared signal or for selectively connecting the match input line to the match output line based on the mask data.
摘要翻译：一种具有以行和列排列的单元阵列的三元内容可寻址存储器（TCAM），每个单元包括用于存储数据位及其补码的主存储单元和用于承载数据位及其补码的一对位线。具有一对比较线和输出节点的比较电路，所述比较电路耦合到主存储器单元，用于将数据位及其补码与对应的比较线进行比较，并在输出节点处输出比较的信号。匹配电路，其耦合到比较电路的输出节点和匹配输入线和匹配输出线，所述匹配电路用于基于所比较的信号选择性地将匹配输入线连接到匹配输出线。用于存储和输出掩模数据的掩模存储单元和耦合到匹配电路和匹配输入线和匹配输出线的屏蔽电路，用于屏蔽比较的信号或者基于该匹配输出线选择性地将匹配输入线连接到匹配输出线掩码数据。

5. 发明授权

US06711040B2 Saving content addressable memory power through conditional comparisons 有权
标题翻译：通过条件比较保存内容可寻址的内存电源
公开(公告)号：US06711040B2
公开(公告)日：2004-03-23
申请号：US10353119
申请日：2003-01-28
申请人： Thomas B. Chadwick , Tari S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Quellette
发明人： Thomas B. Chadwick , Tari S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Quellette
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译：用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。

6. 发明授权

US06707693B1 Content addressable memory with simultaneous write and compare function 有权
标题翻译：内容可寻址内存，具有同时写入和比较功能
公开(公告)号：US06707693B1
公开(公告)日：2004-03-16
申请号：US10163263
申请日：2002-06-05
申请人： Michael E. Ichiriu
发明人： Michael E. Ichiriu
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) device having a simultaneous write and compare function. The CAM device includes a plurality of rows of CAM cells, and match lines and word lines coupled to the rows of CAM cells. The CAM device further includes a plurality of switching circuits coupled to the word lines and the match lines, each switching circuit being adapted to selectively disable assertion of a match signal on a corresponding one of the match lines based, at least in part, on the state of a corresponding one of the word lines.
摘要翻译：一种具有同时写入和比较功能的内容可寻址存储器（CAM）装置。 CAM设备包括多行CAM单元，并且匹配耦合到CAM单元行的行和字线。 CAM设备还包括耦合到字线和匹配线的多个开关电路，每个开关电路适于至少部分地基于所述匹配线选择性地禁用对应的匹配线上的匹配信号的断言相应的一行字线的状态。

7. 发明授权

US06678184B2 CAM cell having compare circuit formed over two active regions 有权
标题翻译： CAM单元具有形成在两个有效区域上的比较电路
公开(公告)号：US06678184B2
公开(公告)日：2004-01-13
申请号：US10163848
申请日：2002-06-05
申请人： Mark A. Lysinger , Christophe Frey , Frederic LaLanne
发明人： Mark A. Lysinger , Christophe Frey , Frederic LaLanne
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.
摘要翻译：公开了具有用于改善CAM单元和CAM阵列的半导体衬底区域利用率的晶体管的物理实现的内容寻址存储器（CAM）单元。 CAM单元包括第一和第二存储器电路和比较电路。六个晶体管的比较电路形成在两个有源区域上。比较电路和由多晶硅区域形成的第一存储器电路之间的局部互连。比较电路和由多晶硅和导电区域形成的第二存储器电路之间的局部互连。

8. 发明授权

US06650561B2 High reliability content-addressable memory using shadow content-addressable memory 有权
标题翻译：高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存
公开(公告)号：US06650561B2
公开(公告)日：2003-11-18
申请号：US10059863
申请日：2002-01-30
申请人： Kevin A. Batson , Geordie M. Braceras , Robert E. Busch , Gary S. Koch
发明人： Kevin A. Batson , Geordie M. Braceras , Robert E. Busch , Gary S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译：使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。阴影CAM与主CAM并行写入，读取和搜索。比较并行搜索的搜索结果，如果相同，则声明为有效。如果搜索结果不相等，则会启动纠正措施。高可靠性内容寻址存储器可以与或不与优先编码器一起使用。

9. 发明授权

US06618281B1 Content addressable memory (CAM) with error checking and correction (ECC) capability 有权
标题翻译：具有错误检查和校正（ECC）能力的内容可寻址存储器（CAM）
公开(公告)号：US06618281B1
公开(公告)日：2003-09-09
申请号：US10146154
申请日：2002-05-15
申请人： Tarl S. Gordon
发明人： Tarl S. Gordon
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G06F11/1064
摘要： A content addressable memory (CAM) and method capable of ignoring and correcting bit errors contained therein is disclosed. In an exemplary embodiment, the CAM includes a plurality of individual CAM cells for storing a codeword having a number of bits associated therewith. A match line is coupled to each of the plurality of individual CAM cells, and is used to indicate a match status of a comparand word that is compared to the stored codeword. The match status is reflective of either a match state or a mismatch state. A sensing apparatus is used for latching the match line to the match state whenever the comparand word mismatches the stored codeword by a number of N or fewer bits, wherein N is defined a maximum number of correctable bits for a given ECC algorithm used.
摘要翻译：公开了能够忽略和校正其中包含的位错误的内容可寻址存储器（CAM）和方法。在示例性实施例中，CAM包括多个单独的CAM单元，用于存储具有与其相关联的位数的码字。匹配线耦合到多个单独CAM单元中的每一个，并且用于指示与存储的码字进行比较的比较字的匹配状态。匹配状态反映了匹配状态或不匹配状态。只要比较字将存储的码字与存储的码字不匹配多个N个或更少位，则使用感测装置将匹配线锁存到匹配状态，其中N被定义为所使用的给定ECC算法的可校正位的最大数量。

10. 发明授权

US06618280B2 Associative memory for accomplishing longest coincidence data detection by two comparing operations 失效
公开(公告)号：US06618280B2
公开(公告)日：2003-09-09
申请号：US10142891
申请日：2002-05-13
申请人： Noriaki Takahashi , Hideaki Odagiri
发明人： Noriaki Takahashi , Hideaki Odagiri
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G11C15/04
摘要： An associative memory includes an array of CAM cells each having a transistor indicating a result from comparing a stored bit with a reference bit. The transistors are connected in serial in each row of the array to form a NAND circuit producing a signal representing that the bits stored in all the cells in the row are consistent with the reference bits or otherwise that the cell at the LSB of the row stores a bit consistent with a reference bit. Each column of the array includes a logic circuit for masking the bits except those continuous from the MSB toward the LSB which correspond to the bits of a word having the most bits continuous from the MSB toward the LSB and consistent with the bits of the reference word among the stored words. The NAND circuit in a row of the cells storing a word having the most bits continuous from the MSB toward the LSB and consistent with the corresponding bits of a reference word develops a signal representing the longest coincidence data detected.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式