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31. 发明授权

US07856562B2 Selective deactivation of processor cores in multiple processor core systems 有权
标题翻译：在多个处理器核心系统中选择性地禁用处理器内核
公开(公告)号：US07856562B2
公开(公告)日：2010-12-21
申请号：US11743341
申请日：2007-05-02
申请人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K. C. Kwan , W. Kurt Lewchuk , Paul Mackey
发明人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K. C. Kwan , W. Kurt Lewchuk , Paul Mackey
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.
摘要翻译：一种方法包括将电压施加到多个处理器核心的第一处理器核心以去激活第一处理器核心，该电压小于第一处理器核心的保持电压。电压的应用可以响应于软件设置。可以通过用户输入，软件应用程序，操作系统或BIOS设置来配置软件设置。或者，电压的施加可以响应于诸如与第一处理器核心相关联的保险丝的状态的永久硬件设置。

32. 发明申请

US20090235099A1 Protocol for Transitioning In and Out of Zero-Power State 有权
标题翻译：零权力转移议定书
公开(公告)号：US20090235099A1
公开(公告)日：2009-09-17
申请号：US12045764
申请日：2008-03-11
申请人： Alexander Branover , Rajen S. Ramchandani
发明人： Alexander Branover , Rajen S. Ramchandani
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A processor may comprise one or more cores, where each respective core may comprise one or more state registers, and non-volatile memory configured to store microcode instructions executed by the respective processor core. The processor may further comprise a power management controller (PMC) interfacing with each respective core, and a state monitor (SM) interfacing with the PMC. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a low-power state. The microcode may communicate the request to the PMC, which may in turn determine if the request is for the respective core to transition to a zero-power state. If it is, the PMC may communicate with the SM to determine whether to transition the respective processor core to the zero-power state, and initiate transition to the zero-power state if a determination to transition to the zero-power state is made.
摘要翻译：处理器可以包括一个或多个核，其中每个相应的核可以包括一个或多个状态寄存器，以及被配置为存储由相应的处理器核执行的微代码指令的非易失性存储器。处理器还可以包括与每个相应核心接口的功率管理控制器（PMC）以及与PMC接口的状态监视器（SM）。 PMC可以被配置为与每个相应的核心进行通信，使得由相应的处理器核心执行的微代码可以识别何时请求将相应的核心转换到低功率状态。微码可以将该请求传送到PMC，PMC可以依次确定该请求是否为相应的核心转换到零功率状态。如果是，则PMC可以与SM进行通信，以确定是否将相应的处理器核心转换到零功率状态，并且如果做出转变到零功率状态的确定，则启动到零功率状态的转变。

33. 发明授权

US5005884A Cylinder lock modified for use with a card reader unlocking mechanism 失效
标题翻译：修改了用于读卡器解锁机构的气缸锁
公开(公告)号：US5005884A
公开(公告)日：1991-04-09
申请号：US474395
申请日：1990-02-06
申请人： Aaron M. Fish , Alexander Branover , Jean-Paul Dausseing , Masoud Miresmaili
发明人： Aaron M. Fish , Alexander Branover , Jean-Paul Dausseing , Masoud Miresmaili
IPC分类号： E05B15/00 , E05B17/22 , E05B55/00
CPC分类号： E05B55/005 , E05B17/22 , Y10S292/37 , Y10T292/03 , Y10T292/57 , Y10T70/8027
摘要： The pushing in of the push-button of the cylinder lock is detected by detecting the associated motion of the locking rod. An electronic signal is provided upon the detection of such motion. In specific embodiments, the detector consists of a switch mounted on either the locking rod or locking rod cylinder, and an associated cam mounted on either the locking rod cylinder or the locking rod.
摘要翻译：通过检测锁定杆的相关联的运动来检测气缸锁的按钮的推入。在检测到这种运动时提供电子信号。在具体实施例中，检测器由安装在锁定杆或锁定杆气缸上的开关以及安装在锁定杆气缸或锁定杆上的相关凸轮组成。

34. 发明授权

US08966305B2 Managing processor-state transitions 有权
标题翻译：管理处理器状态转换
公开(公告)号：US08966305B2
公开(公告)日：2015-02-24
申请号：US13174144
申请日：2011-06-30
申请人： Alexander Branover , Maurice B. Steinman , John P. Petry
发明人： Alexander Branover , Maurice B. Steinman , John P. Petry
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state.
摘要翻译：公开了关于管理空闲功率状态的进入和退出的功耗和延迟的技术。在一个实施例中，处理器包括被配置为在包括操作功率状态和至少一个空闲功率状态的多个功率状态（例如，C状态）中操作的处理核心。处理核心还被配置为在多个执行状态下操作。处理器还包括功率管理单元，其被配置为从处理核心接收进入至少一个空闲功率状态的请求。功率管理单元被配置为基于所请求的空闲功率状态来选择多个性能状态中的第一个（例如，P状态）。在一个实施例中，功率管理单元还被配置为使得处理核心在进入所请求的空闲功率状态之前转变到所选择的第一执行状态。

35. 发明授权

US08447994B2 Altering performance of computational units heterogeneously according to performance sensitivity 有权
标题翻译：根据性能敏感性改变计算单元的性能不均匀
公开(公告)号：US08447994B2
公开(公告)日：2013-05-21
申请号：US12508929
申请日：2009-07-24
申请人： Sebastien Nussbaum , Alexander Branover , John Kalamatianos
发明人： Sebastien Nussbaum , Alexander Branover , John Kalamatianos
IPC分类号： G05B13/02 , G06F1/00
CPC分类号： G06F1/324 , Y02D10/126
摘要： One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.
摘要翻译：计算机系统的一个或多个计算单元在性能方面被选择性地改变，根据所述一个或多个计算单元中的哪一个具有比其他计算单元更高的性能灵敏度。

36. 发明授权

US08438416B2 Function based dynamic power control 有权
标题翻译：基于功能的动态功率控制
公开(公告)号：US08438416B2
公开(公告)日：2013-05-07
申请号：US12909006
申请日：2010-10-21
申请人： Andrej Kocev , Alexander Branover
发明人： Andrej Kocev , Alexander Branover
IPC分类号： G06F1/32 , G06F1/10
CPC分类号： G06F1/3237 , G06F1/3275 , G06F1/3287 , Y02D10/128 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.
摘要翻译：公开了一种用于基于动态功能的功率控制的系统和方法。在一个实施例中，系统包括具有存储器控制器和耦合到存储器控制器的通信集线器的桥接单元。该系统还包括电力管理单元，其中电力管理单元被配置为响应于确定多个处理器核心中的每一个处于空闲状态并且I / O接口单元已经空闲而对通信集线器进行时钟门超过第一阈值的时间量。电源管理单元还被配置为响应于时钟门控通信集线器来对存储器控制器进行时钟门控，并且确定耦合到存储器控制器的存储器处于第一低功率状态。功率管理单元还可以在其门控门控之后执行功能单元的功率门控。

37. 发明授权

US08412971B2 Method and apparatus for cache control 有权
标题翻译：用于缓存控制的方法和装置
公开(公告)号：US08412971B2
公开(公告)日：2013-04-02
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/26
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

38. 发明申请

US20130007494A1 MANAGING PROCESSOR-STATE TRANSITIONS 有权
标题翻译：管理处理器状态转换
公开(公告)号：US20130007494A1
公开(公告)日：2013-01-03
申请号：US13174144
申请日：2011-06-30
申请人： Alexander Branover , Maurice B. Steinman , John P. Petry
发明人： Alexander Branover , Maurice B. Steinman , John P. Petry
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state.
摘要翻译：公开了关于管理空闲功率状态的进入和退出的功耗和延迟的技术。在一个实施例中，处理器包括被配置为在包括操作功率状态和至少一个空闲功率状态的多个功率状态（例如，C状态）中操作的处理核心。处理核心还被配置为在多个执行状态下操作。处理器还包括功率管理单元，其被配置为从处理核心接收进入至少一个空闲功率状态的请求。功率管理单元被配置为基于所请求的空闲功率状态来选择多个性能状态中的第一个（例如，P状态）。在一个实施例中，功率管理单元还被配置为使得处理核心在进入所请求的空闲功率状态之前转变到所选择的第一执行状态。

39. 发明申请

US20110113202A1 CACHE FLUSH BASED ON IDLE PREDICTION AND PROBE ACTIVITY LEVEL 有权
标题翻译：基于空闲预测和探测活动级别的缓存缓冲
公开(公告)号：US20110113202A1
公开(公告)日：2011-05-12
申请号：US12702085
申请日：2010-02-08
申请人： Alexander Branover , Maurice B. Steinman
发明人： Alexander Branover , Maurice B. Steinman
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.
摘要翻译：处理节点跟踪与其高速缓存相关联的探测活动级别。处理节点和/或处理系统进一步预测空闲持续时间。如果探测器活动级别增加到高于阈值探测器活动级别，并且空闲持续时间预测高于阈值空闲持续时间阈值，则处理节点刷新其高速缓存以防止对高速缓存的探测。如果探测器活动级别高于阈值探测器活动级别，但是预测的空闲持续时间太短，则处理节点的性能状态增加到其当前的性能状态以提供增强的响应探测请求的性能能力。

40. 发明申请

US20110022833A1 ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY 有权
标题翻译：根据性能敏感性改变计算单位的性能异常
公开(公告)号：US20110022833A1
公开(公告)日：2011-01-27
申请号：US12508929
申请日：2009-07-24
申请人： Sebastien Nussbaum , Alexander Branover , John Kalamatianos
发明人： Sebastien Nussbaum , Alexander Branover , John Kalamatianos
IPC分类号： G06F9/00 , G06F1/26 , G06F15/76 , G06F9/02
CPC分类号： G06F1/324 , Y02D10/126
摘要： One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.
摘要翻译：计算机系统的一个或多个计算单元在性能方面被选择性地改变，根据所述一个或多个计算单元中的哪一个具有比其他计算单元更高的性能灵敏度。

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