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1. 发明授权

US08438416B2 Function based dynamic power control 有权
标题翻译：基于功能的动态功率控制
公开(公告)号：US08438416B2
公开(公告)日：2013-05-07
申请号：US12909006
申请日：2010-10-21
申请人： Andrej Kocev , Alexander Branover
发明人： Andrej Kocev , Alexander Branover
IPC分类号： G06F1/32 , G06F1/10
CPC分类号： G06F1/3237 , G06F1/3275 , G06F1/3287 , Y02D10/128 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.
摘要翻译：公开了一种用于基于动态功能的功率控制的系统和方法。在一个实施例中，系统包括具有存储器控制器和耦合到存储器控制器的通信集线器的桥接单元。该系统还包括电力管理单元，其中电力管理单元被配置为响应于确定多个处理器核心中的每一个处于空闲状态并且I / O接口单元已经空闲而对通信集线器进行时钟门超过第一阈值的时间量。电源管理单元还被配置为响应于时钟门控通信集线器来对存储器控制器进行时钟门控，并且确定耦合到存储器控制器的存储器处于第一低功率状态。功率管理单元还可以在其门控门控之后执行功能单元的功率门控。

2. 发明申请

US20120102344A1 FUNCTION BASED DYNAMIC POWER CONTROL 有权
标题翻译：基于功能的动态功率控制
公开(公告)号：US20120102344A1
公开(公告)日：2012-04-26
申请号：US12909006
申请日：2010-10-21
申请人： Andrej Kocev , Alexander Branover
发明人： Andrej Kocev , Alexander Branover
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/3275 , G06F1/3287 , Y02D10/128 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.
摘要翻译：公开了一种用于基于动态功能的功率控制的系统和方法。在一个实施例中，系统包括具有存储器控制器和耦合到存储器控制器的通信集线器的桥接单元。该系统还包括电力管理单元，其中电力管理单元被配置为响应于确定多个处理器核心中的每一个处于空闲状态并且I / O接口单元已经空闲而对通信集线器进行时钟门超过第一阈值的时间量。电源管理单元还被配置为响应于时钟门控通信集线器来对存储器控制器进行时钟门控，并且确定耦合到存储器控制器的存储器处于第一低功率状态。功率管理单元还可以在其门控门控之后执行功能单元的功率门控。

3. 发明申请

US20080288751A1 TECHNIQUE FOR PREFETCHING DATA BASED ON A STRIDE PATTERN 有权
标题翻译：基于矩阵模式预测数据的技术
公开(公告)号：US20080288751A1
公开(公告)日：2008-11-20
申请号：US11750266
申请日：2007-05-17
申请人： Andrej Kocev
发明人： Andrej Kocev
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/383 , G06F9/3455 , G06F12/0862 , G06F2212/1021 , G06F2212/6026
摘要： A processor system (100) includes a central processing unit (102) and a prefetch engine (110). The prefetch engine (110) is coupled to the central processing unit (102). The prefetch engine (110) is configured to detect, when data associated with the central processing unit (102) is read from a memory (114), a stride pattern in an address stream based upon whether sums of a current stride and a previous stride are equal for a number of consecutive reads. The prefetch engine (110) is also configured to prefetch, for the central processing unit (102), data from the memory (114) based on the detected stride pattern.
摘要翻译：处理器系统（100）包括中央处理单元（102）和预取引擎（110）。预取引擎（110）耦合到中央处理单元（102）。预取引擎（110）被配置为当基于当前步幅和先前步幅的和时，当从存储器（114）读取与中央处理单元（102）相关联的数据时，检测地址流中的步幅图案对于多个连续的读数是相等的。预取引擎（110）还被配置为基于检测到的步幅模式为中央处理单元（102）预取来自存储器（114）的数据。

4. 发明申请

US20080235485A1 ECC implementation in non-ECC components 有权
标题翻译： ECC实现在非ECC组件中
公开(公告)号：US20080235485A1
公开(公告)日：2008-09-25
申请号：US11725922
申请日：2007-03-20
申请人： Michael John Haertel , R. Stephen Polzin , Andrej Kocev , Maurice Bennet Steinman
发明人： Michael John Haertel , R. Stephen Polzin , Andrej Kocev , Maurice Bennet Steinman
IPC分类号： G06F12/00
CPC分类号： G06F11/1044
摘要： A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.
摘要翻译：用于在非ECC兼容组件中实现纠错码（ECC）检查的方法和装置。该方法包括接收逻辑地址，其中逻辑地址映射到存储器的第一和第二物理地址。存储器的第一和第二物理地址分别对应于存储数据的存储器位置和对应的ECC。该方法还包括将逻辑地址转换为第一和第二物理地址，通过数据路径访问数据，通过相同数据路径分别访问ECC，以及使用ECC检查数据的完整性。

5. 发明申请

US20050060473A1 Method and system of completing pending I/O device reads in a multiple-processor computer system 有权
标题翻译：在多处理器计算机系统中完成未完成的I / O设备读取的方法和系统
公开(公告)号：US20050060473A1
公开(公告)日：2005-03-17
申请号：US10662782
申请日：2003-09-15
申请人： Samuel Duncan , Andrej Kocev , David Mayo
发明人： Samuel Duncan , Andrej Kocev , David Mayo
IPC分类号： G06F13/14 , G06F13/24 , G06F13/32
CPC分类号： G06F13/24 , G06F2213/0024
摘要： A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system.
摘要翻译：一种用于通过在多处理器计算机系统中的程序周期性地停止I / O设备访问的发布来完成未完成的I / O设备读取的方法和系统。

6. 发明授权

US06701387B1 Adaptive data fetch prediction algorithm 有权
标题翻译：自适应数据提取预测算法
公开(公告)号：US06701387B1
公开(公告)日：2004-03-02
申请号：US09652644
申请日：2000-08-31
申请人： Roger Pannel , David W. Hartwell , Samuel H. Duncan , Rajen Ramchandani , Andrej Kocev , Jeffrey Willcox , Steven Ho
发明人： Roger Pannel , David W. Hartwell , Samuel H. Duncan , Rajen Ramchandani , Andrej Kocev , Jeffrey Willcox , Steven Ho
IPC分类号： G06F1300
CPC分类号： G06F12/0862 , G06F13/28
摘要： A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.
摘要翻译：一种用于通过DMA连接到多处理器系统网格的PCI协议I / O设备来适应DMA读请求的速度要求的方法和装置。描述了设备控制器和网格之间的桥接器，其将来自数据的数据的缓存行中的数据从数据缓存到I / O设备。该系统是自适应的，因为过去读取中所需的高速缓存行的数量被记住并用于确定高速缓存行的数量是减少还是增加。

7. 发明授权

US08135935B2 ECC implementation in non-ECC components 有权
标题翻译： ECC实现在非ECC组件中
公开(公告)号：US08135935B2
公开(公告)日：2012-03-13
申请号：US11725922
申请日：2007-03-20
申请人： Michael John Haertel , R. Stephen Polzin , Andrej Kocev , Maurice Bennet Steinman
发明人： Michael John Haertel , R. Stephen Polzin , Andrej Kocev , Maurice Bennet Steinman
IPC分类号： G06F12/10 , G06F11/08
CPC分类号： G06F11/1044
摘要： A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.
摘要翻译：用于在非ECC兼容组件中实现纠错码（ECC）检查的方法和装置。该方法包括接收逻辑地址，其中逻辑地址映射到存储器的第一和第二物理地址。存储器的第一和第二物理地址分别对应于存储数据的存储器位置和对应的ECC。该方法还包括将逻辑地址转换为第一和第二物理地址，通过数据路径访问数据，通过相同数据路径分别访问ECC，以及使用ECC检查数据的完整性。

8. 发明授权

US07831800B2 Technique for prefetching data based on a stride pattern 有权
标题翻译：基于步幅模式预取数据的技术
公开(公告)号：US07831800B2
公开(公告)日：2010-11-09
申请号：US11750266
申请日：2007-05-17
申请人： Andrej Kocev
发明人： Andrej Kocev
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3455 , G06F12/0862 , G06F2212/1021 , G06F2212/6026
摘要： A processor system (100) includes a central processing unit (102) and a prefetch engine (110). The prefetch engine (110) is coupled to the central processing unit (102). The prefetch engine (110) is configured to detect, when data associated with the central processing unit (102) is read from a memory (114), a stride pattern in an address stream based upon whether sums of a current stride and a previous stride are equal for a number of consecutive reads. The prefetch engine (110) is also configured to prefetch, for the central processing unit (102), data from the memory (114) based on the detected stride pattern.
摘要翻译：处理器系统（100）包括中央处理单元（102）和预取引擎（110）。预取引擎（110）耦合到中央处理单元（102）。预取引擎（110）被配置为当基于当前步幅和先前步幅的和时，当从存储器（114）读取与中央处理单元（102）相关联的数据时，检测地址流中的步幅图案对于多个连续的读数是相等的。预取引擎（110）还被配置为基于检测到的步幅模式为中央处理单元（102）预取来自存储器（114）的数据。

9. 发明申请

US20080295097A1 Techniques for sharing resources among multiple devices in a processor system 审中-公开
标题翻译：用于在处理器系统中的多个设备之间共享资源的技术
公开(公告)号：US20080295097A1
公开(公告)日：2008-11-27
申请号：US11753355
申请日：2007-05-24
申请人： Andrej Kocev
发明人： Andrej Kocev
IPC分类号： G06F9/46
CPC分类号： G06F9/5011
摘要： A technique of shared resource handling for multiple devices includes determining a first lifetime of a first transaction associated with an active first device, included within the multiple devices. The technique also includes assigning at least a portion of a first system resource to the active first device for use in the first transaction, when the first lifetime corresponds to a long-lifetime. Finally, the technique includes assigning at least a portion of a second system resource to the active first device for use in the first transaction, when the first lifetime corresponds to a short-lifetime. In this case, the second system resource was previously reserved to one or more inactive second devices, included within the multiple devices.
摘要翻译：用于多个设备的共享资源处理技术包括确定包括在多个设备内的与活动的第一设备相关联的第一事务的第一生命周期。该技术还包括当第一寿命对应于长寿命时，将第一系统资源的至少一部分分配给活动的第一设备以供在第一事务中使用。最后，当第一寿命对应于短寿命时，该技术包括将第二系统资源的至少一部分分配给活动的第一设备以供在第一事务中使用。在这种情况下，第二系统资源先前被保留给包括在多个设备内的一个或多个不活动的第二设备。

10. 发明授权

US07099978B2 Method and system of completing pending I/O device reads in a multiple-processor computer system 有权
标题翻译：在多处理器计算机系统中完成未完成的I / O设备读取的方法和系统
公开(公告)号：US07099978B2
公开(公告)日：2006-08-29
申请号：US10662782
申请日：2003-09-15
申请人： Samuel H. Duncan , Andrej Kocev , David T. Mayo
发明人： Samuel H. Duncan , Andrej Kocev , David T. Mayo
IPC分类号： G06F13/32 , G06F13/24
CPC分类号： G06F13/24 , G06F2213/0024
摘要： A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system.
摘要翻译：一种用于通过在多处理器计算机系统中的程序周期性地停止I / O设备访问的发布来完成未完成的I / O设备读取的方法和系统。

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