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31. 发明申请

US20120317523A1 Reducing Through Process Delay Variation in Metal Wires 有权
标题翻译：通过金属线的过程延迟变化减少
公开(公告)号：US20120317523A1
公开(公告)日：2012-12-13
申请号：US13157909
申请日：2011-06-10
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.
摘要翻译：提供了一种通过布局重新定位来减少金属线中的工艺延迟变化的机制。该机制执行初始重定向，分解和分辨率增强技术。例如，该机构可以执行光学邻近校正。该机制进行光刻模拟和光学规则检查。该机制提供了基于耦合光刻模拟和电阻/电容（RC）提取开发的重定向规则。该机制执行RC提取以捕获RC对设计形状尺寸的非线性依赖性。如果光刻仿真中的电性能在预定义的规格范围内，则该机制接受重定向规则; 然而，如果来自RC提取的电性能超出预定义的规范，则该机制修改重定向规则并重复分辨率增强技术。

32. 发明授权

US08176444B2 Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance 有权
标题翻译：分析多个诱导的系统和统计布局对电路性能的影响
公开(公告)号：US08176444B2
公开(公告)日：2012-05-08
申请号：US12426475
申请日：2009-04-20
申请人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
发明人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
摘要翻译：一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

33. 发明申请

US20110154280A1 PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY 有权
标题翻译：传播设计公差以形成平面图
公开(公告)号：US20110154280A1
公开(公告)日：2011-06-23
申请号：US12640129
申请日：2009-12-17
申请人： Kanak Agarwal , Shayak Banerjee , Sani Nassif , Chin Ngai Sze
发明人： Kanak Agarwal , Shayak Banerjee , Sani Nassif , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G06F2217/12 , Y02P90/265
摘要： An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.
摘要翻译：提供了一种计算与硬件设计布局中包括的多个形状相对应的电延迟范围的方法。电延迟范围被转换成每个形状的形状公差。使用形状公差产生硬件设计布局的光刻掩模，使得所生成的掩模中的形状的图像位于对应于相应形状的形状公差内。

34. 发明申请

US20110119642A1 Simultaneous Photolithographic Mask and Target Optimization 有权
标题翻译：同时光刻掩模和目标优化
公开(公告)号：US20110119642A1
公开(公告)日：2011-05-19
申请号：US12619742
申请日：2009-11-17
申请人： Kanak B. Agarwal , Shayak Banerjee , Damir A. Jamsek
发明人： Kanak B. Agarwal , Shayak Banerjee , Damir A. Jamsek
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F1/36
摘要： A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements.
摘要翻译：提供了用于同时光刻掩模和目标优化（SMATO）的机制。光刻模拟器在晶片上产生掩模形状的图像，从而形成一个或多个平版印刷轮廓。掩模和目标移动模块分析地评估掩模和目标移动的方向，从而形成多对掩模和目标移动。掩模和目标移动模块从多个掩模和目标移动中识别出最佳化加权成本函数的最佳对掩模和目标移动。形状调整模块基于最佳的一对掩模和目标移动来调整目标形状或掩模形状中的至少一个。

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