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    • 34. 发明授权
    • Test apparatus and synchronization method
    • 测试仪器和同步方法
    • US08700964B2
    • 2014-04-15
    • US13029065
    • 2011-02-16
    • Tatsuya Yamada
    • Tatsuya Yamada
    • G01R31/28
    • G01R31/31726G01R31/31922
    • A test apparatus that tests a device under test, including (i) a master domain that includes a master period signal generating section, which generates a master period signal, where the master domain operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, where the slave domain operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is on hold, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is on hold.
    • 一种测试被测设备的测试装置,包括:(i)包括主周期信号产生部分的主域,其产生主时段信号,其中主域基于主周期信号操作,以及(ii)从属 域,其包括从周期信号生成部分,其产生从周期信号,其中从属域基于从周期信号操作。 主周期信号发生部分接收控制信号并恢复保持的主周期信号的产生,从周期信号产生部分接收控制信号,初始化从周期信号的相位数据,并恢复生成 从周期信号,其保持。
    • 35. 发明授权
    • Test apparatus and test method
    • 试验装置及试验方法
    • US08502523B2
    • 2013-08-06
    • US13024264
    • 2011-02-09
    • Tatsuya Yamada
    • Tatsuya Yamada
    • G01R23/00
    • G01R31/31922
    • Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains. The test apparatus comprises a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain.
    • 提供了一种用于基本上同步多个时钟域中的每一个的测试信号的相位的测试装置和测试方法。 测试装置测试包括多个时钟域的被测器件。 测试装置包括周期发生器,其产生用于确定对应于被测器件的操作周期的测试周期的速率信号; 生成测试图案的图案生成器; 相位比较部,对于每个时钟域,接收从被包括在时钟域中的被测器件的端子获取的时钟域的操作时钟信号,并且相对于时钟域的操作时钟信号的相位差相对于 到速率信号; 以及多个波形整形部分,分别设置在时钟域上,并且根据相应的时钟域的相位差,基于测试图形来形成测试信号,以使测试信号与操作时钟基本上同步 相应时钟域的信号。
    • 37. 发明授权
    • Pattern generation for test apparatus and electronic device
    • 测试仪器和电子设备的图案生成
    • US07725793B2
    • 2010-05-25
    • US11689506
    • 2007-03-21
    • Tatsuya YamadaTomoyuki Sugaya
    • Tatsuya YamadaTomoyuki Sugaya
    • G01R31/28G06F11/00
    • G01R31/31919G01R31/31813
    • There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed, a pattern generating section that (i) sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction and (II) timing set information designating a combination of timings for output of the test pattern, (ii) under a condition of executing the subroutine call instruction, sequentially reads and executes an instruction from the sub test instruction sequence designated by the executed subroutine call instruction and outputs (1) a test pattern associated with the executed instruction and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence, and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information.
    • 提供了一种用于测试被测设备的测试装置。 测试装置包括:主指令存储部分,其上存储有主测试指令序列;子指令存储部分,其存储当执行包括在主测试指令序列中的子程序调用指令时执行的子测试指令序列; (i)顺序读取并执行来自主测试指令序列的指令,并且输出(I)与所执行的指令相关联的测试模式;以及(II)指定用于输出测试模式的定时的组合的定时设置信息 ,(ii)在执行子程序调用指令的条件下,顺序地从由执行的子程序调用指令指定的子测试指令序列读取并执行指令,并输出(1)与执行的指令相关联的测试模式,(2) 与子程序调用指令相关联的测试模式的定时设置信息或 在主测试指令序列中的子程序调用指令之前的指令以及根据测试模式产生测试信号的测试信号输出部分,并且在由定时设定的定时将测试信号提供给被测器件 信息。
    • 38. 发明授权
    • Control apparatus for AC-AC converter
    • AC-AC转换器控制装置
    • US07696730B2
    • 2010-04-13
    • US11882283
    • 2007-07-31
    • Yasuhiro TamaiTatsuya Yamada
    • Yasuhiro TamaiTatsuya Yamada
    • H02J3/08H02J3/00
    • H02M5/27
    • A control apparatus for an AC-AC direct converter. The control apparatus includes a calculator providing a phase command θ* of an output voltage of the converter, a calculator providing a q-axis current iq by using output currents iu and iw and the phase command θ*, a detector detecting a pulsation component contained in the q-axis current iq, a calculator providing a phase correction magnitude θcmp so as to decrease the pulsation component, and an adder/subtractor correcting the phase command θ* by using the correction magnitude θcmp. This apparatus can decrease the output voltage distortion and low frequency torque pulsation and can suppress the increase of an output current without weakening a magnetic flux, even when the converter is operated in an overmodulation region.
    • 一种用于AC-AC直接转换器的控制装置。 控制装置包括:计算器,其提供转换器的输出电压的相位指令和*,通过使用输出电流iu和iw以及相位指令&等提供q轴电流iq的计算器; *,检测脉动的检测器 分量包含在q轴电流iq中,计算器提供相位校正幅度& cmp,以减小脉动分量;以及加法器/减法器,通过使用校正幅度& cmp校正相位指令。 该装置可以降低输出电压失真和低频转矩脉动,并且即使当转换器在过调制区域中操作时也可以抑制输出电流的增加而不削弱磁通量。
    • 39. 发明申请
    • TEST APPARATUS AND ELECTRONIC DEVICE
    • 测试装置和电子设备
    • US20080250291A1
    • 2008-10-09
    • US11733174
    • 2007-04-09
    • Tatsuya YamadaKiyoshi Murata
    • Tatsuya YamadaKiyoshi Murata
    • G01R31/3183
    • G01R31/31813
    • A test apparatus that tests a device under test is provided.The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.
    • 提供测试被测设备的测试设备。 测试装置包括:模式存储器,以压缩格式存储测试指令序列,以定义用于测试被测设备的测试序列; 扩展部分块以非压缩格式扩展从模式存储器读取的测试指令序列; 缓存由扩展部扩展的测试指令序列的指令高速缓存; 模式生成部,其顺序地读取存储在所述指令高速缓存中的指令,并执行所述指令,以生成所执行的指令的测试模式; 以及信号输出部,其基于测试图案生成测试信号,并将其提供给被测设备。
    • 40. 发明申请
    • Control apparatus for AC-AC converter
    • AC-AC转换器控制装置
    • US20080055955A1
    • 2008-03-06
    • US11882283
    • 2007-07-31
    • Yasuhiro TamaiTatsuya Yamada
    • Yasuhiro TamaiTatsuya Yamada
    • H02M5/293
    • H02M5/27
    • A control apparatus for an AC-AC direct converter. The control apparatus includes a calculator providing a phase command θ* of an output voltage of the converter, a calculator providing a q-axis current iq by using output currents iu and iw and the phase command θ*, a detector detecting a pulsation component contained in the q-axis current iq, a calculator providing a phase correction magnitude θcmp so as to decrease the pulsation component, and an adder/subtractor correcting the phase command θ* by using the correction magnitude θcmp. This apparatus can decrease the output voltage distortion and low frequency torque pulsation and can suppress the increase of an output current without weakening a magnetic flux, even when the converter is operated in an overmodulation region.
    • 一种用于AC-AC直接转换器的控制装置。 控制装置包括一个计算器,它提供转换器输出电压的相位指令θ*,一个通过使用输出电流i 提供q轴电流i 和相位指令θ*,检测器,其检测包含在q轴电流i Q q中的脉动分量,提供相位校正幅度θ cmp ,以便减小脉动分量,以及加法器/减法器,通过使用校正幅度θcmp 校正相位指令θ*。 该装置可以降低输出电压失真和低频转矩脉动,并且即使当转换器在过调制区域中操作时也可以抑制输出电流的增加而不削弱磁通量。