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1. 发明申请

US20190235019A1 MEMORY CIRCUIT MARCH TESTING 审中-公开
公开(公告)号：US20190235019A1
公开(公告)日：2019-08-01
申请号：US15882674
申请日：2018-01-29
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： Thomas Ziaja , Lancelot Kwong
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31724 , G01R31/31813 , G01R31/3183 , G01R31/318555
摘要： Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.

2. 发明授权

US09869716B2 Device comprising programmable logic element 有权
公开(公告)号：US09869716B2
公开(公告)日：2018-01-16
申请号：US14612745
申请日：2015-02-03
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki Kurokawa
IPC分类号： G01R31/28 , G11C29/36 , H01L27/06 , G01R31/3181 , G11C11/16 , H01L27/10
CPC分类号： G01R31/2884 , G01R31/31813 , G11C11/16 , G11C29/36 , G11C2029/3602 , H01L27/0688 , H01L27/101
摘要： Provided is a device capable of generating test patterns even after the design stage. The area of a circuit which is included in the device and unnecessary during normal operation can be reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit. The fourth circuit has a function of storing a first data and a function of storing a second data. The fifth circuit has a function of writing the first data to the plurality of fourth circuits, a function of writing the second data to the plurality of fourth circuits, and a function of reading the second data from the plurality of fourth circuits.

3. 发明申请

US20160299189A1 TESTING A FEEDBACK SHIFT-REGISTER 有权
标题翻译：测试反馈移位寄存器
公开(公告)号：US20160299189A1
公开(公告)日：2016-10-13
申请号：US15038617
申请日：2013-11-28
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： Göran SELANDER , Mats NÄSLUND , Elena DUBROVA
IPC分类号： G01R31/317 , G11C29/02 , G01R31/3177 , G11C19/28
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/3177 , G01R31/31813 , G01R31/318547 , G11C19/28 , G11C29/02 , G11C29/021
摘要： A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR may be tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. This may not increase the propagation delay of the original design, and the resulting dynamic power dissipation during test can be considerably less than known BIST designs.
摘要翻译：提供了一种能够改进测试的反馈移位寄存器（FSR），例如内置自检（BIST）。 FSR的每个单元可以是可观察的单元，其与由组合逻辑电路实现的非平凡的反馈功能相关联，或者具有相关联的状态变量的可控单元，微不足道的反馈功能。每个可控单元设置有用于选择可控单元的前导单元或测试值作为输入的多路复用器。因此，可以使用用于组合逻辑的测试来测试FSR的顺序电路。所公开的测试程序使用最小的一组测试向量，并允许检测FSR中所有单个卡住的故障。这可能不会增加原始设计的传播延迟，并且测试期间产生的动态功耗可能远远低于已知的BIST设计。

4. 发明授权

US09256503B2 Data verification 有权
标题翻译：数据验证
公开(公告)号：US09256503B2
公开(公告)日：2016-02-09
申请号：US14075969
申请日：2013-11-08
申请人： Ivan Selivanov
发明人： Ivan Selivanov
IPC分类号： G06F11/00 , G06F11/263 , G01R31/3181
CPC分类号： G06F11/263 , G01R31/31813
摘要： A data verification application receives a test configuration data, the test configuration data comprising a seed value and a parameter. The data verification application generates a pseudo-random test data stream comprising a plurality of words, wherein a value of each of the plurality of words is based on the seed value, the parameter and an offset of each word within the pseudo-random test data stream.
摘要翻译：数据验证应用程序接收测试配置数据，测试配置数据包括种子值和参数。数据验证应用产生包括多个单词的伪随机测试数据流，其中多个单词中的每一个的值基于种子值，伪随机测试数据内的每个单词的参数和偏移量流。

5. 发明授权

US09170301B1 Hierarchical compaction for test pattern power generation 有权
标题翻译：测试模式发电的分层压实
公开(公告)号：US09170301B1
公开(公告)日：2015-10-27
申请号：US13772245
申请日：2013-02-20
申请人： Cadence Design Systems, Inc.
发明人： Patrick Gallagher , Krishna Chakravadhanula , Rajesh Khurana
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3177
CPC分类号： G01R31/31813 , G01R31/3177 , G01R31/318544 , G01R31/318575
摘要： A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.
摘要翻译：公开了一种用于在测试期间应用于集成电路的测试图案的分层压缩的方法和装置。这些实施例应用分级策略来分类用于压实的测试模式。针对压实测试模式的一系列标准考虑了测试模式。在满足所有标准的情况下，测试图案被合并到压实的测试图案中。如果不满足标准，则依次对每个压实的测试模式考虑测试模式。对于每个测试图案重复这一点，以创建符合标准要求的一组压实测试图案。该方法和装置在测试集成电路时提供对低功率约束的细粒度控制，并且包括诸如防止在烧坏和热点期间的测试期间的损坏以及避免由于IR下降引起的故障的益处。

6. 发明申请

US20150302126A1 TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS 有权
标题翻译：用便携式场景模型和不同级别测试SOC
公开(公告)号：US20150302126A1
公开(公告)日：2015-10-22
申请号：US14689596
申请日：2015-04-17
申请人： Breker Verification Systems
发明人： Adnan Hamid , Kairong Qian , Kieu Do
IPC分类号： G06F17/50
CPC分类号： G01R31/3177 , G01R31/31813 , G06F3/0484 , G06F9/4881 , G06F11/2205 , G06F11/25 , G06F11/263 , G06F11/3688 , G06F17/5009 , G06F17/5027 , G06F17/5068 , G06T11/206
摘要： A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
摘要翻译：描述了一种用于测试片上系统（SoC）的方法。该方法包括解析文件以确定要执行SoC的组件的功能。所述方法还包括接收所述SoC的所需输出并且基于所述SoC的期望输出生成测试场景模型。测试场景模型包括功能的多个模块表示，并且包括两个模块表示之间的一个或多个连接。所需的输出作为测试场景模型的性能约束。测试场景模型还包括基于期望输出，模块表示和一个或多个连接生成的SoC的输入。测试场景模型包括从输入通过模块表示的路径和到期望输出的连接。

7. 发明申请

US20130166979A1 Methods and Systems for an Automated Test Configuration to Identify Logic Device Defects 有权
标题翻译：用于识别逻辑器件缺陷的自动测试配置的方法和系统
公开(公告)号：US20130166979A1
公开(公告)日：2013-06-27
申请号：US13546793
申请日：2012-07-11
申请人： Angel SOCARRAS
发明人： Angel SOCARRAS
IPC分类号： G01R31/3177
CPC分类号： G01R31/31813
摘要： Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.
摘要翻译：提供了一种被配置用于测试逻辑设备的装置。该装置包括测试机构，其被配置为输出表示逻辑设备内的逻辑结构的测试模式，以及可测试逻辑设备，其具有（i）输入端口耦合到自动测试机构的输出端口，以及（ii）输出端口耦合到输入端口自动化测试机制。该装置还包括一个熔断机构，其被配置为补偿逻辑装置内的缺陷，以响应所识别的缺陷类型的偏析。

8. 发明申请

US20130159803A1 ASYNCHRONOUS CIRCUIT WITH AN AT-SPEED BUILT-IN SELF-TEST (BIST) ARCHITECTURE 有权
标题翻译：具有快速内置自检（BIST）架构的异步电路
公开(公告)号：US20130159803A1
公开(公告)日：2013-06-20
申请号：US13327847
申请日：2011-12-16
申请人： Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
发明人： Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/3187
摘要： Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.
摘要翻译：公开了集成电路的实施例，该集成电路结合具有内置自检（BIST）架构的异步电路，使用用于高速测试的握手协议来检测卡住故障。在实施例中，测试模式发生器将测试模式应用于异步电路，分析器分析输出测试数据。握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换的测试模式确认信号。可以通过切换测试模式确认信号来强制产生该单个脉冲。可选地，可以将时间约束添加到捕获输出测试数据以允许检测延迟故障。

9. 发明申请

US20130091382A1 Modeling Test Space for System behavior with Optional Variable combinations 有权
标题翻译：使用可选的变量组合建模系统行为的测试空间
公开(公告)号：US20130091382A1
公开(公告)日：2013-04-11
申请号：US13253089
申请日：2011-10-05
申请人： Itai Segall , Rachel Tzoref-Brill , Aviad Zlotnick
发明人： Itai Segall , Rachel Tzoref-Brill , Aviad Zlotnick
IPC分类号： G06F11/28
CPC分类号： G06F11/3676 , G01R31/3181 , G01R31/31813 , G01R31/3183 , G01R31/318314 , G01R31/31835 , G01R31/318357 , G01R31/318364 , G06F11/3684
摘要： A method for modeling a test space is provided. The method comprises defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and one or more definitions for value combinations for said variables with assigned values, wherein at least one of said value combinations is defined as optional, and zero or more other said value combinations are defined as forbidden or mandatory for purpose of generating test scenarios to test a system for which the coverage model is defined.
摘要翻译：提供了一种用于建模测试空间的方法。该方法包括定义覆盖模型，包括：一个或多个变量，其中分配变量的相应值，以及用于具有分配值的所述变量的值组合的一个或多个定义，其中所述值组合中的至少一个被定义为可选的，并且零个或多个其他所述值组合被定义为禁止或强制的，用于生成测试场景以测试覆盖模型被定义的系统。

10. 发明申请

US20130035891A1 TEST PATTERN GENERATOR, METHOD OF GENERATING TEST PATTERN, AND COMPUTER READABLE STORAGE MEDIUM HAVING TEST GENERATION PROGRAM STORED THEREON 审中-公开
标题翻译：测试模式发生器，测试模式的生成方法，以及存储有测试生成程序的计算机可读存储介质
公开(公告)号：US20130035891A1
公开(公告)日：2013-02-07
申请号：US13463885
申请日：2012-05-04
申请人： Daisuke Maruyama
发明人： Daisuke Maruyama
IPC分类号： G06F19/00 , G01R31/3183
CPC分类号： G01R31/31813
摘要： A second computing device determines whether or not a conflict occurs wherein at least two of a plurality of first computing devices set different request values to an input point to which a request value is to be set, based on the request value stored in the request value buffer. When it is determined by the second computing device that a conflict occurs wherein one of the plurality of first computing devices is about to set a request value different from a request value that is set to that input point by another first computing device, the one of the first computing devices stops setting the request value. This prevents any increase in the test pattern count due to parallel processing.
摘要翻译：第二计算设备基于存储在请求值中的请求值来确定是否发生冲突，其中多个第一计算设备中的至少两个设置不同请求值到要设置请求值的输入点缓冲。当由第二计算设备确定发生冲突时，其中多个第一计算设备中的一个即将设置与另一第一计算设备设置为该输入点的请求值不同的请求值，第一计算设备停止设置请求值。这可以防止由于并行处理而导致的测试图案计数的任何增加。

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