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    • 31. 发明申请
    • WIRELESS COMMUNICATION METHOD WITHOUT PAIRING IDENTITIES IN ADVANCE AND DEVICE THEREOF
    • 无线通信方法,无前提下的配对标识及其设备
    • US20170055107A1
    • 2017-02-23
    • US14848361
    • 2015-09-09
    • Beken Corporation
    • Lizhen ZhuRonghui KongBo Jia
    • H04W4/00H04L1/16
    • H04W4/80H04L1/16
    • A wireless communication method without pairing IDs in advance, comprises: transmitting, at a first power, a first ID within a first pipe; searching for a second ID on at least one frequency point, wherein the second ID matches the first ID; if the second ID is not found within the first pipe, respectively transmitting, at least at a second power and a third power, at least two matching-code requests within a public pipe on public frequency points; receiving ACKs responding to each of the matching-code requests from different devices; summing numbers of the received ACKs from each device; comparing the summed numbers of the received ACKs from the different devices to get a maximum number; switching from a public pipe to a third pipe of a device that sent the maximum number of ACKs; transmitting a matching-code package to the device that sent the maximum number of ACKs.
    • 预先不配对ID的无线通信方法包括:以第一功率发送第一管道内的第一ID; 在至少一个频点上搜索第二ID,其中所述第二ID与所述第一ID匹配; 如果在第一管道内没有发现第二ID,则至少在第二功率和第三功率下分别在公共频点上的公共管道内发送至少两个匹配码请求; 接收响应于来自不同设备的每个匹配码请求的ACK; 从每个设备求和接收的ACK数; 比较来自不同设备的接收到的ACK的总和数以获得最大数量; 从公共管道切换到发送最大数量的ACK的设备的第三个管道; 向发送最大数量的ACK的设备发送匹配码包。
    • 32. 发明授权
    • Calibration circuit and method
    • 校准电路及方法
    • US09401690B2
    • 2016-07-26
    • US14191440
    • 2014-02-27
    • Beken Corporation
    • Dawei GuoJianqin Zheng
    • H03H11/16H03H7/48
    • H03H7/48
    • A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output.
    • 电路包括相位合成器和四个输出端口。 相位合成器加上同相正输入和正交正输入以获得同相正输出,相加负输入和正交负输入以获得同相负输出,将同相相加 负输入和正交正输入以获得正交正输出,并且将同相正输入和正交负输入相加以获得正交负输出。 四个输出端口分别配置为输出同相正输出,同相负输出,正交正输出和正交负输出。
    • 35. 发明授权
    • Phase locked loop circuit and a method in the phase locked loop circuit
    • 锁相环电路和锁相环电路中的一种方法
    • US08766685B1
    • 2014-07-01
    • US13911099
    • 2013-06-06
    • Beken Corporation
    • Yunfeng ZhaoRonghui KongDawei Guo
    • H03L7/06H03L7/08
    • H03L7/104
    • A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.
    • PLL电路包括相位频率检测器(PFD),电荷泵(CP),低通滤波器(LPF),压控振荡器(VCO),分频器(FD)和复位模块。 PFD接收第一和第二输入信号,并根据第一和第二输入信号之间的相位和频率差输出第一和第二调整参数。 CP耦合到PFD,根据第一和第二调整参数产生电流。 LPF耦合到CP,并根据电流产生电压。 VCO耦合到LPF,并根据电压产生振荡频率。 FD接收并分频振荡频率,并产生第二输入信号。 复位模块产生复位信号以馈送到FD,其中复位模块接收第一信号。
    • 36. 发明授权
    • Amplitude shift keying demodulator and method for demodulating an ask signal
    • 幅移键控解调器和解调询问信号的方法
    • US08508293B2
    • 2013-08-13
    • US13405632
    • 2012-02-27
    • Jiazhou LiuDawei GuoYangeng Wang
    • Jiazhou LiuDawei GuoYangeng Wang
    • H03K9/02
    • H04L27/06H03D1/2272
    • An ASK demodulator comprises a rectification circuit which receives and rectifies an ASK signal to generate a rectified current; an active load circuit is coupled to the rectification circuit and receives the rectified current and present an impedance which is inversely proportional to at least a part of the rectified current when a frequency of a base band signal meets a preset condition; a comparator is coupled to the rectification circuit and the active load circuit and receives a reference voltage and a voltage generated based on, at least in part, the rectified current and the impedance, and compares the reference voltage and the generated voltage to generate a demodulated signal.
    • ASK解调器包括整流电路,其接收并整流ASK信号以产生整流电流; 有源负载电路耦合到整流电路,并且当基带信号的频率满足预设条件时,接收整流电流并呈现与至少一部分整流电流成反比的阻抗; 比较器耦合到整流电路和有源负载电路,并且接收基准电压和至少部分地基于整流电流和阻抗产生的电压,并且比较参考电压和产生的电压以产生解调的 信号。