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1. 发明申请

US20190229711A1 CLOCK DISTRIBUTION 审中-公开
公开(公告)号：US20190229711A1
公开(公告)日：2019-07-25
申请号：US16244025
申请日：2019-01-09
申请人： Socionext Inc.
发明人： Sylvain PANIER , Behzad Farzaneh , Darren Walker , Ian Juso Dedic
IPC分类号： H03K3/012 , H03K3/017 , G06F1/10
CPC分类号： H03K3/012 , G06F1/10 , H03K3/017 , H03K5/086 , H03K5/1565
摘要： Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.

2. 发明申请

US20190200444A1 ELECTRICAL PULSE GENERATOR 审中-公开
公开(公告)号：US20190200444A1
公开(公告)日：2019-06-27
申请号：US16326740
申请日：2017-08-24
申请人： CLARTEIS
发明人： Sounil BHOSLE
IPC分类号： H05H1/24 , H03K3/037 , H03K19/20 , H03K3/012
CPC分类号： H05H1/2406 , H03K3/012 , H03K3/037 , H03K3/57 , H03K19/20
摘要： The invention relates to a pulse generator comprising an inductor that is intended to store energy that is delivered, during a charge phase, by a DC voltage source to two power supply terminals of the generator, and to transfer the energy to the dielectric-barrier discharge device during a discharge phase via a transformer, the generator further comprising: an arrangement of a first and of a second circuits in series that are connected at a node N of the generator; the first circuit comprising two branches, one of the two branches comprising the inductor, and the other branch comprising a diode and the transformer, the secondary being connected to the dielectric-barrier discharge device; the second circuit comprising a controlled switch.

3. 发明申请

US20190173472A1 CLOCK GATING CIRCUIT 审中-公开
公开(公告)号：US20190173472A1
公开(公告)日：2019-06-06
申请号：US16259631
申请日：2019-01-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ah-Reum KIM , Hyun LEE , Min-su KIM
IPC分类号： H03K19/0185 , H03K3/356 , H03K3/037 , H03K19/00 , H03K3/012
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/037 , H03K3/356104 , H03K3/356191 , H03K19/0013
摘要： Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

4. 发明申请

US20190109582A1 Pulse Triggered Flip Flop 审中-公开
公开(公告)号：US20190109582A1
公开(公告)日：2019-04-11
申请号：US16180604
申请日：2018-11-05
申请人： Intel Corporation
发明人： Bhushan M. Borole , Anupama A. Thaploo , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
IPC分类号： H03K3/012 , H03K3/356 , H03K19/21
CPC分类号： H03K3/012 , H03K3/356 , H03K3/35606 , H03K19/215
摘要： A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

5. 发明申请

US20190028091A1 Clock Gating Circuit 审中-公开
公开(公告)号：US20190028091A1
公开(公告)日：2019-01-24
申请号：US15658214
申请日：2017-07-24
申请人： ARM Limited
发明人： Anil Kumar Baratam , Nruthya Nagesh Prabhu , Yves Thomas Laplanche
IPC分类号： H03K3/356 , H03K17/687
CPC分类号： H03K3/356121 , H03K3/012 , H03K17/6872
摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

6. 发明申请

US20180351537A1 ASYNCHRONOUS CLOCK GATING CIRCUIT 审中-公开
公开(公告)号：US20180351537A1
公开(公告)日：2018-12-06
申请号：US15573907
申请日：2016-06-14
申请人： INVECAS TECHNOLOGIES PVT. LTD
发明人： GYAN PRAKASH , NIDHIR KUMAR
IPC分类号： H03K3/012 , H03K3/037
CPC分类号： H03K3/012 , H03K3/037 , H03K3/0375 , H03K5/135 , H03K19/0016
摘要： The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of cluck gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.

7. 发明申请

US20180301327A1 A CIRCUIT FOR GENERATING A VOLTAGE WAVEFORM AT AN OUTPUT NODE 审中-公开
公开(公告)号：US20180301327A1
公开(公告)日：2018-10-18
申请号：US15569492
申请日：2016-03-24
申请人： SHIMADZU CORPORATION
发明人： Steven Douglas TAYLOR , Stuart John Lawrence HARLEY , John HANDFORD
IPC分类号： H01J49/02 , H03K3/012 , H03K17/687
CPC分类号： H01J49/022 , H02M7/537 , H02M2001/0058 , H02M2007/4815 , H03K3/012 , H03K17/6874 , Y02B70/1441 , Y02B70/1491
摘要： A circuit for generating a voltage waveform at an output node. The circuit includes a first voltage rail configured to be held at a first voltage, wherein the first voltage rail is connected to the output node via a first voltage rail switch; a second voltage rail configured to be held at a second voltage that is different from the first voltage, wherein the second voltage rail is connected to the output node via a second voltage rail switch; at least one anchor node connected to the output node via an inductor and an anchor node switch; and a control unit configured to switch the circuit between: a first voltage outputting state in which the first voltage rail switch is closed and the second voltage rail switch is open such that the output node is clamped to the first voltage; and a second voltage outputting producing state in which the second voltage rail switch is closed and the first voltage rail switch is open such that the output node is clamped to the second voltage. The control unit is configured to switch the circuit from the first voltage outputting state to the second voltage outputting state by: opening the first voltage rail switch and closing an anchor node switch that connects the output node via an inductor to an anchor node held at a first anchor voltage so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance causing the voltage at the output node to swing towards the second voltage, wherein the first anchor voltage is configured to provide energy that assists the voltage at the output node in swinging towards the second voltage; and then opening the anchor node switch and closing the second voltage rail switch. The control unit is further configured to switch the circuit from the second voltage outputting state to the first voltage outputting state by: opening the second voltage rail switch and closing an anchor node switch that connects the output node via an inductor to an anchor node held at a second anchor voltage so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance causing the voltage at the output node to swing towards the first voltage, wherein the second anchor voltage is configured to provide energy that assists the voltage at the output node in swinging towards the first voltage; and then opening the anchor node switch and closing the first voltage rail switch.

8. 发明申请

US20180269858A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180269858A1
公开(公告)日：2018-09-20
申请号：US15686921
申请日：2017-08-25
申请人： SK hynix Inc.
发明人： Kyung Whan KIM , Dong Uk LEE
IPC分类号： H03K3/012 , H03K5/134
CPC分类号： H03K3/012 , G01R31/317 , H03K5/06 , H03K5/134 , H03K2005/00019 , H03K2005/00195
摘要： A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.

9. 发明授权

US10062680B2 Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods 有权
公开(公告)号：US10062680B2
公开(公告)日：2018-08-28
申请号：US14272981
申请日：2014-05-08
申请人： QUALCOMM Incorporated
发明人： Pratyush Kamal , Yang Du
IPC分类号： H01L27/02 , H01L27/092 , H01L27/12 , H03K3/012 , H01L29/78 , H01L29/786
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/1203 , H01L29/7831 , H01L29/78696 , H03K3/012
摘要： Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.

10. 发明申请

US20180226969A1 MULTI-LEVEL ADIABATIC CHARGING METHODS, DEVICES AND SYSTEMS 审中-公开
公开(公告)号：US20180226969A1
公开(公告)日：2018-08-09
申请号：US15887178
申请日：2018-02-02
申请人： The Regents of the University of California
发明人： Loai Galal Bahgat Salem , Patrick Mercier
IPC分类号： H03K19/00 , H03K3/012 , G11C5/14 , G11C11/4074 , H03K19/096 , H03K19/017
CPC分类号： H03K19/0019 , G11C5/147 , G11C11/4074 , H03K3/012 , H03K19/017 , H03K19/0963
摘要： A method for adiabatic charging of a capacitive load sequentially connects outer switches between a voltage VDD and ground and inner switches to at least one capacitance that self-balances between VDD and ground. A voltage waveform is provided to the capacitive load from a common node of the outer switches and the inner switches. An adiabatic charging circuit includes outer transistor switches between a voltage VDD and ground. Inner transistor switches are connected to at least one capacitance that self-balances between VDD and ground. A control signal generating circuit generates control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at a common node of the inner and outer transistor switches.

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