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1. 发明申请

US20190089363A1 FREQUENCY LOCKED LOOP WITH FAST VOLTAGE/FREQUENCY TRANSITION 审中-公开
公开(公告)号：US20190089363A1
公开(公告)日：2019-03-21
申请号：US16134599
申请日：2018-09-18
申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives
发明人： Ivan MIRO PANADES
IPC分类号： H03L7/099 , G06F1/10
CPC分类号： H03L7/0992 , G06F1/08 , G06F1/10 , G06F1/324 , G06F1/3296 , H03L7/104
摘要： The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal of the processing core and comprising a frequency locked loop having: a digitally controlled oscillator configured to generate the variable frequency clock signal; and a controller (614) configured to generate a digital control signal (C_FREQ), wherein the controller is configured to implement a frequency transition of the variable frequency clock signal from a first frequency to a second lower frequency by generating: a first value of the digital control signal (C_FREQ) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency lower than the second frequency; and further values of the digital control signal (C_FREQ).

2. 发明申请

US20170310328A1 SIGNAL GENERATION CIRCUIT AND SIGNAL GENERATION METHOD 审中-公开
公开(公告)号：US20170310328A1
公开(公告)日：2017-10-26
申请号：US15491552
申请日：2017-04-19
申请人： CANON KABUSHIKI KAISHA
发明人： Koji Ishibashi
IPC分类号： H03L7/089 , H03L7/099 , H03L7/093
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/099 , H03L7/104 , H03L7/1075 , H03L7/18
摘要： A signal generation circuit comprises a VCO configured to generate a signal with a frequency corresponding to a control voltage; a divider configured to generate a divided signal by dividing the frequency of the signal generated by the VCO; a phase comparator configured to compare a reference clock signal generated by a reference oscillator and the divided signal generated by the divider; a charge pump configured to output a current corresponding to a comparison result of the phase comparator; a loop filter configured to generate a voltage corresponding to the current output by the charge pump; a switched capacitor filter configured to generate, by sampling the voltage generated by the loop filter, a control voltage of the VCO in a steady state; and an initial-value provision circuit configured to provide an initial value of the control voltage of the VCO.

3. 发明授权

US09490819B2 Auto frequency calibration for a phase locked loop and method of use 有权
标题翻译：锁相环的自动频率校准和使用方法
公开(公告)号：US09490819B2
公开(公告)日：2016-11-08
申请号：US14603900
申请日：2015-01-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yen-Jen Chen , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03L7/06 , H03L7/08 , H03L7/10 , H03L7/197 , G04F10/00 , H03L7/085 , H03L7/099 , H03M1/00
CPC分类号： H03L7/0802 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/0992 , H03L7/101 , H03L7/103 , H03L7/104 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M3/32
摘要： An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.
摘要翻译：一种装置，包括代码发生器，其被配置为基于参考频率和相位差信号产生粗调谐信号和复位信号。该装置还包括数字环路滤波器，其配置为基于相位差信号产生微调信号。该装置还包括电压控制振荡器，被配置为基于粗调谐信号和微调信号产生输出信号。该装置还包括分配器，其被配置为基于分频器控制信号和输出信号产生分频器频率。相位差信号至少部分地基于分频器，并且分频器被配置为基于复位信号被复位。

4. 发明申请

US20160191067A1 OSCILLATOR WITH FREQUENCY CONTROL LOOP 有权
标题翻译：具有频率控制环的振荡器
公开(公告)号：US20160191067A1
公开(公告)日：2016-06-30
申请号：US14587951
申请日：2014-12-31
申请人： Texas Instruments Incorporated
发明人： Sreekiran Samala , Vineet Mishra , Mahadevan Shankara Venkiteswaran
IPC分类号： H03L7/099 , H03B5/24
CPC分类号： H03L7/0995 , H03B5/24 , H03K3/0231 , H03L1/026 , H03L7/095 , H03L7/099 , H03L7/104 , H03L7/18
摘要： Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit.
摘要翻译：提供振荡输出信号的电路。电路包括具有第一输入，第二输入和输出的跨导电路。电路还包括耦合以从跨导电路的输出接收电压的振荡器电路，其中振荡输出信号响应振荡器电路的输出。还包括用于向跨导电路的第一输入提供第一电压的电路和用于向第二输入提供跨导电路的第二电压的频率控制电路。第二电压响应于频率控制电路的工作频率，并且频率控制电路的工作频率响应于来自振荡器电路的输出的反馈。

5. 发明授权

US09337850B2 All-digital phase-locked loop (ADPLL) with reduced settling time 有权
标题翻译：全数字锁相环（ADPLL），降低了建立时间
公开(公告)号：US09337850B2
公开(公告)日：2016-05-10
申请号：US14446568
申请日：2014-07-30
申请人： NXP B.V.
发明人： Ulrich Moehlmann
IPC分类号： H03L7/06 , H03L7/099
CPC分类号： H03L7/0994 , H03L7/099 , H03L7/0991 , H03L7/104 , H03L2207/06 , H03L2207/50
摘要： Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.
摘要翻译：锁相环（ADPLL）可以减少或消除建立时间。振荡器模型提供适用于补偿频率响应和相位响应的适当设置。硬件设备可以包括数字控制振荡器（DCO）; 以及具有处理器的DCO模型设备，其中所述处理器被配置为通过基于所述DCO的操作参数搜索所述频率来计算所述DCO的频率，将所计算的频率与测量的频率进行比较，并且基于所述比较来补偿，ADPLL来减少建立时间。

6. 发明授权

US09281822B2 Oscillator 有权
标题翻译：振荡器
公开(公告)号：US09281822B2
公开(公告)日：2016-03-08
申请号：US14485812
申请日：2014-09-15
申请人： NIHON DEMPA KOGYO CO., LTD.
发明人： Tomoya Yorita
IPC分类号： H03B5/32 , H03L1/02 , H03L7/06 , H03L7/14 , H03L7/099 , H03L7/10
CPC分类号： H03L1/02 , H03B5/32 , H03L1/026 , H03L7/099 , H03L7/0991 , H03L7/104 , H03L7/145
摘要： An oscillator includes a voltage controlled oscillator, a PLL circuit, a crystal unit and an oscillator circuit configured to generate a clock, a digital control circuit, and a clock switching unit. The digital control circuit is configured to set an oscillation parameter of the oscillator circuit, and a parameter of the PLL circuit. The clock switching unit is configured to supply an output signal of the voltage controlled oscillator to the digital control circuit as a clock signal so as to cause the digital control circuit to operate using the clock signal when powered on, and configured to supply an output signal of the oscillator circuit to the digital control circuit as a clock signal after the digital control circuit sets the oscillation parameter of the oscillator circuit. An initial voltage is supplied to the voltage controlled oscillator as a control voltage when the oscillator is powered on.
摘要翻译：振荡器包括压控振荡器，PLL电路，晶体单元和被配置为产生时钟的振荡器电路，数字控制电路和时钟切换单元。数字控制电路被配置为设置振荡电路的振荡参数和PLL电路的参数。时钟切换单元被配置为将压控振荡器的输出信号作为时钟信号提供给数字控制电路，以使数字控制电路在通电时使用时钟信号进行操作，并且被配置为提供输出信号的振荡器电路作为数字控制电路的时钟信号，在数字控制电路设置振荡器电路的振荡参数之后。当振荡器通电时，初始电压作为控制电压提供给压控振荡器。

7. 发明授权

US09071255B2 Phase locked loop and associated phase alignment method 有权
标题翻译：锁相环和相关相位对准方法
公开(公告)号：US09071255B2
公开(公告)日：2015-06-30
申请号：US13609749
申请日：2012-09-11
申请人： Cheng-Chieh Lin , Jian-Yu Ding , Yao-Chi Wang
发明人： Cheng-Chieh Lin , Jian-Yu Ding , Yao-Chi Wang
IPC分类号： H03L7/197 , H03L7/099 , H03L7/10
CPC分类号： H03L7/1976 , H03L7/099 , H03L7/104 , H03L2207/06
摘要： A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.
摘要翻译：提供了锁相环和相关对准方法。所公开的锁相环接收参考信号以提供反馈信号。首先打开锁相环。当锁相环断开时，基本上选择来自压控振荡器的振荡信号的频率范围。根据振荡信号提供反馈信号。选择频率范围后，锁相环保持断开，参考信号和反馈信号的相位基本对齐。然后在参考信号和反馈信号对齐后，闭锁环路。

8. 发明申请

US20150180485A1 APPARATUS AND METHODS FOR FREQUENCY LOCK ENHANCEMENT OF PHASE-LOCKED LOOPS 有权
标题翻译：相位锁定机构的频率锁定增强装置及方法
公开(公告)号：US20150180485A1
公开(公告)日：2015-06-25
申请号：US14134767
申请日：2013-12-19
申请人： Analog Devices Technology
发明人： Hyman Shanan , Michael F. Keaveney
IPC分类号： H03L7/099 , H03L7/093
CPC分类号： H03L7/099 , H03L1/026 , H03L7/104
摘要： Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.
摘要翻译：提供了锁相环（PLL）的频率锁定增强的装置和方法。在一个方面，PLL可以包括具有调谐电压输入的VCO和被配置为设置VCO的频带设置的频率调谐电路。频率调谐电路可以包括电压监视器，其被配置为将调谐电压输入的电压电平与一个或多个调谐电压阈值电平进行比较，控制电路被配置为至少控制VCO的频带设置和偏置电流设置，以及振幅检测电路，被配置为将VCO的振荡信号的振幅与一个或多个振幅阈值电平进行比较。

9. 发明申请

US20150102860A1 OSCILLATION CIRCUIT, OSCILLATOR, ELECTRONIC DEVICE, AND MOVING OBJECT 有权
标题翻译：振荡电路，振荡器，电子设备和移动对象
公开(公告)号：US20150102860A1
公开(公告)日：2015-04-16
申请号：US14514816
申请日：2014-10-15
申请人： Seiko Epson Corporation
发明人： Yuichi TORIUMI , Nobutaka SHIOZAKI
IPC分类号： H03L7/099
CPC分类号： H03L7/197 , H03L7/104 , H03L7/1974
摘要： An oscillation circuit, an oscillator, an electronic device, and a moving object which are capable of adjusting an output frequency in a high modulation bandwidth with a high level of accuracy and adjusting a timing at which the output frequency is changed are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element and includes a communication unit that receives frequency setting data for setting a frequency of the oscillation signal and frequency change data which is given a timing at which the frequency of the oscillation signal is changed on the basis of the frequency setting data, by serial transfer, and registers in which the frequency setting data and the frequency change data received by the communication unit are stored, respectively. An address of the register storing the frequency setting data is continuous with an address of the register storing the frequency change data.
摘要翻译：提供能够以高精度调整高调制带宽的输出频率并调整输出频率变化的定时的振荡电路，振荡器，电子设备和运动物体。振荡电路通过振荡振荡元件产生振荡信号，并包括通信单元，该通信单元接收用于设定振荡信号的频率的频率设定数据和给予振荡信号的频率变化的定时的频率变化数据通过串行传送的频率设置数据的基础，以及分别存储通信单元接收的频率设置数据和频率变化数据的寄存器。存储频率设定数据的寄存器的地址与存储频率变化数据的寄存器的地址连续。

10. 发明授权

US09008254B2 Method and apparatus for suppressing a deterministic clock jitter 有权
标题翻译：用于抑制确定性时钟抖动的方法和装置
公开(公告)号：US09008254B2
公开(公告)日：2015-04-14
申请号：US14014445
申请日：2013-08-30
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang Lin
IPC分类号： H03D3/24 , H03L7/08
CPC分类号： H03L7/104 , H03L7/093
摘要： A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.
摘要翻译：一种用于产生输出时钟的方法，包括：检测第一输入时钟与第二输入时钟之间的定时差以产生相位误差信号; 通过基于确定性抖动指示符信号掩蔽相位误差信号来产生掩蔽相位误差信号; 通过对掩蔽的相位误差信号进行滤波来产生振荡器控制信号; 并根据振荡器控制信号产生输出时钟。

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