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31. 发明申请

US20110317480A1 PHASE CHANGE MEMORY CODING 有权
标题翻译：相变存储器编码
公开(公告)号：US20110317480A1
公开(公告)日：2011-12-29
申请号：US12823508
申请日：2010-06-25
申请人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

32. 发明授权

US08084295B2 Thin film transistor having n-type and p-type CIS thin films and method of manufacturing the same 失效
标题翻译：具有n型和p型CIS薄膜的薄膜晶体管及其制造方法
公开(公告)号：US08084295B2
公开(公告)日：2011-12-27
申请号：US12938833
申请日：2010-11-03
申请人： Sang Su Lee , Kibong Song , Jeong Dae Suh , Keongam Kim , Doo-Hee Cho
发明人： Sang Su Lee , Kibong Song , Jeong Dae Suh , Keongam Kim , Doo-Hee Cho
IPC分类号： H01L21/06
CPC分类号： H01L29/78681 , H01L29/24
摘要： Provided is a thin film transistor (TFT) which uses CIS (CuInSe2), including Se, which is a chalcogen-based material, and can provide a rectifying function, and electric and optical switching functions of a diode. The TFT according to the present invention includes, a substrate, a gate electrode formed on a portion of the substrate, an insulating layer covering the substrate and a gate electrode, a plurality of CIS (CuInSe2) films formed on the insulating layer so as to cover the region where the gate electrode is formed; and source/drain regions separated from each other so as to comprise a trench exposing a portion of a surface of the CIS films.
摘要翻译：提供了使用CIS（CuInSe2）的薄膜晶体管（TFT），其包括作为硫属元素材料的Se，并且可以提供二极管的电和光开关功能。根据本发明的TFT包括：基板，形成在基板的一部分上的栅电极，覆盖基板的绝缘层和栅极电极，形成在绝缘层上的多个CIS（CuInSe 2）膜，以便覆盖形成栅电极的区域; 和源极/漏极区域彼此分离，以便包括暴露CIS膜表面的一部分的沟槽。

33. 发明申请

US20110263075A1 Vacuum Jacket For Phase Change Memory Element 有权
标题翻译：相变存储元件真空护套
公开(公告)号：US20110263075A1
公开(公告)日：2011-10-27
申请号：US12911554
申请日：2010-10-25
申请人： Hsiang Lan Lung
发明人： Hsiang Lan Lung
IPC分类号： H01L21/06
CPC分类号： H01L45/148 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , Y10S438/90
摘要： A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.
摘要翻译：一种包括相变元件和真空护套的存储器件。该装置包括第一电极元件; 与所述第一电极元件接触的相变元件; 与所述相变元件接触的上电极元件; 与上电极元件接触的位线电极; 以及围绕所述相变元件和所述上电极元件的介电填充层，与所述相位元件和所述上电极元件间隔开并且由所述位线电极密封以在所述相变元件和上电极元件周围限定真空护套。

34. 发明授权

US08030128B1 Method to form high density phase change memory (PCM) top contact every two bits 有权
标题翻译：每两位形成高密度相变存储器（PCM）顶部接触的方法
公开(公告)号：US08030128B1
公开(公告)日：2011-10-04
申请号：US12104215
申请日：2008-04-16
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L21/06
CPC分类号： H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： Embodiments of the present invention provide a method that includes providing a substrate including an emitter layer comprising a plurality of emitters, each emitter defining an axis, forming a heater layer above the emitter layer, and forming a phase change memory (PCM) cell layer above the heater layer. The method also includes forming a top contact layer above the PCM cell layer. The top contact layer comprises a plurality of top contacts, where each top contact is located between two axes. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种方法，其包括提供包括包括多个发射器的发射极层的基板，每个发射极限定轴线，在发射极层上方形成加热器层，以及形成上述相变存储器（PCM）单元层加热器层。该方法还包括在PCM单元层上形成顶部接触层。顶部接触层包括多个顶部接触件，其中每个顶部接触件位于两个轴线之间。还描述了其它实施例。

35. 发明申请

US20110223716A1 ELECTRICAL DEVICE USING PHASE CHANGE MATERIAL, PHASE CHANGE MEMORY DEVICE USING SOLID STATE REACTION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：使用相变材料的电气设备，使用固态反应的相变存储器件及其制造方法
公开(公告)号：US20110223716A1
公开(公告)日：2011-09-15
申请号：US13110579
申请日：2011-05-18
申请人： Seung Yun LEE , Young Sam PARK , Sung Min YOON , Soon Won JUNG , Byoung Gon YU
发明人： Seung Yun LEE , Young Sam PARK , Sung Min YOON , Soon Won JUNG , Byoung Gon YU
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1666
摘要： Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed.
摘要翻译：提供了一种非易失性存储器件及其制造方法，其中使用固态反应形成相变层以减少可编程体积，从而降低功耗。该装置包括第一反应物层，形成在第一反应物层上的第二反应物层和由形成第一反应物层的材料与第一反应物层之间的固态反应形成在第一和第二反应物层之间的相变层形成第二反应物层的材料。相变存储器件消耗低功率并以高速运行。

36. 发明授权

US07951676B2 Semiconductor device and method for the production of a semiconductor device 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US07951676B2
公开(公告)日：2011-05-31
申请号：US12201371
申请日：2008-08-29
申请人： Gerhard Schmidt
发明人： Gerhard Schmidt
IPC分类号： H01L29/76 , H01L21/06
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/1095 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/7397 , H01L29/7811
摘要： The semiconductor device has a semiconductor body with a semiconductor device structure. The semiconductor device structure has a first electrode, a second electrode and a gate electrode. The gate electrode is designed to form a conductive channel region. An insulating layer at least partially surrounds the gate electrode. A semi-insulating layer is provided between the gate electrode and at least one of the first electrode and the second electrode. The semi-insulating layer is located outside the conductive channel region and has an interface state density which is greater than the quotient of the breakdown charge and the band gap of the material of the semiconductor body.
摘要翻译：半导体器件具有半导体器件结构的半导体本体。半导体器件结构具有第一电极，第二电极和栅电极。栅电极被设计成形成导电沟道区域。绝缘层至少部分地围绕栅电极。在栅电极和第一电极和第二电极中的至少一个之间提供半绝缘层。半绝缘层位于导电沟道区域的外部，并且具有大于击穿电荷和半导体本体的材料的带隙的商的界面态密度。

37. 发明授权

US07943420B1 Single mask adder phase change memory element 有权
标题翻译：单掩模加法器相变存储元件
公开(公告)号：US07943420B1
公开(公告)日：2011-05-17
申请号：US12625855
申请日：2009-11-25
申请人： Matthew J. Breitwisch , Chung Hon Lam
发明人： Matthew J. Breitwisch , Chung Hon Lam
IPC分类号： H01L21/06
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/143 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：一种制造半导体结构内的相变存储元件的方法以及具有这样的半导体结构的方法，该方法包括蚀刻对底部电极的上表面的开口，所述开口由与形成的金属区域的高度相等的高度形成在半导体结构内的相同层的电介质层内，在开口内沉积共形膜并使保形膜凹陷以暴露底部电极的上表面，将相变材料沉积在开口内，使相变材料在内打开并在凹陷相变材料上形成顶部电极。

38. 发明申请

US20110110148A1 MEMORY ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING 有权
标题翻译：存储器阵列和相关的制造方法
公开(公告)号：US20110110148A1
公开(公告)日：2011-05-12
申请号：US12617501
申请日：2009-11-12
申请人： Jun Liu
发明人： Jun Liu
IPC分类号： G11C11/00 , H01L21/06 , H01L47/00 , H01L21/20
CPC分类号： H01L45/141 , G11C5/063 , G11C13/0004 , G11C13/0023 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/1691
摘要： Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit.
摘要翻译：本文公开了存储器阵列和相关的制造方法。在一个实施例中，存储器阵列包括沿着第一方向延伸的访问线和沿着不同于第一方向的第二方向延伸的第一接触线和第二接触线。第一和第二接触线通常彼此平行。存储器阵列还包括存储器节点，其包括电连接在接入线路和第一接触线路之间以形成第一电路的第一存储器单元，以及电连接在接入线路和第二接触线路之间的第二存储器单元，第二电路不同于第一电路。

39. 发明申请

US20110070690A1 THERMAL MANAGEMENT AND METHOD FOR LARGE SCALE PROCESSING OF CIS AND/OR CIGS BASED THIN FILMS OVERLYING GLASS SUBSTRATES 有权
公开(公告)号：US20110070690A1
公开(公告)日：2011-03-24
申请号：US12953721
申请日：2010-11-24
申请人： Robert D. Wieting
发明人： Robert D. Wieting
IPC分类号： H01L21/06
CPC分类号： H01L31/0322 , H01L31/03923 , H01L31/1876 , Y02E10/541 , Y02P70/521
摘要： The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the present invention provides a method for fabricating a copper indium diselenide semiconductor film. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, the second temperature ranging from about 350° C. to about 450° C. to at least initiate formation of a copper indium diselenide film from the copper and indium composite structure on each of the substrates.

40. 发明申请

US20110049456A1 PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY 审中-公开
标题翻译：用于相变记忆的复合掺杂相变结构
公开(公告)号：US20110049456A1
公开(公告)日：2011-03-03
申请号：US12553784
申请日：2009-09-03
申请人： HSIANG-LAN LUNG , CHIEH-FANG CHEN , YEN-HAO SHIH , HUAI-YU CHENG , ERH-KUN LAI , MING HSIU LEE , MATTHEW J. BREITWISCH , SIMONE RAO , CHUNG HON LAM
发明人： HSIANG-LAN LUNG , CHIEH-FANG CHEN , YEN-HAO SHIH , HUAI-YU CHENG , ERH-KUN LAI , MING HSIU LEE , MATTHEW J. BREITWISCH , SIMONE RAO , CHUNG HON LAM
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1641
摘要： A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region.
摘要翻译：使用在第一电极和第二电极之间的复合掺杂相变材料来描述存储器件。相变材料的存储元件，例如硫族化物，位于第一和第二电极之间并且具有有源区。相变材料具有第一掺杂剂，例如氧化硅，其特征在于倾向于在有源区域中的晶界上与相变材料分离，并且具有第二掺杂剂，例如硅，其特征在于引起再结晶温度的增加的和/或抑制活性区域中的相变材料中的空隙形成。

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