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1. 发明授权

US08689162B2 Method and apparatus for timing closure 失效
标题翻译：用于定时关闭的方法和装置
公开(公告)号：US08689162B2
公开(公告)日：2014-04-01
申请号：US13235908
申请日：2011-09-19
申请人： Jason T. Su , Winston Lee
发明人： Jason T. Su , Winston Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84 , H03K5/159 , H03K2005/00013
摘要： Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.
摘要翻译：本公开的方面提供了诸如集成电路的电路。电路包括第一电路和第二电路。第二电路包括延迟电路，其被配置为响应于制造，环境和操作参数（例如过程变化，温度变化和电源电压）的至少一个参数变化，使得第二电路具有基本匹配的第一电路的延迟特性变异。

2. 发明授权

US08609528B1 High-density patterning 失效
标题翻译：高密度图案化
公开(公告)号：US08609528B1
公开(公告)日：2013-12-17
申请号：US13204370
申请日：2011-08-05
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816
摘要： Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.
摘要翻译：本文描述了用于图案化高密度特征的方法。本发明的实施例提供了一种方法，包括对图案的第一子集进行图案化，所述第一子集被配置成在所述衬底上形成多个线，以及图案化所述图案的第二子集，所述第二子集被配置为形成多个岛其中所述图案化所述第一子集并且所述图案化所述第二子集包括至少两个单独的图案化操作。

3. 发明授权

US08605534B2 Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes 有权
公开(公告)号：US08605534B2
公开(公告)日：2013-12-10
申请号：US12878703
申请日：2010-09-09
申请人： Winston Lee , Ha Soo Kim
发明人： Winston Lee , Ha Soo Kim
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/02 , G11C8/08
摘要： Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.

4. 发明授权

US08335878B2 Multiport memory architecture, devices and systems including the same, and methods of using the same 有权
标题翻译：多端口存储器架构，包括相同的器件和系统以及使用它们的方法
公开(公告)号：US08335878B2
公开(公告)日：2012-12-18
申请号：US12494076
申请日：2009-06-29
申请人： Winston Lee , Sehat Sutardja , Donald Pannell
发明人： Winston Lee , Sehat Sutardja , Donald Pannell
IPC分类号： G06F7/00 , G11C11/401
CPC分类号： G11C7/1075
摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
摘要翻译：多端口内存架构，系统包括相同以及使用方法。架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。系统通常包括体现本文公开的一个或多个发明构思的系统。所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用消除FIFO。本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。

5. 发明授权

US08203902B2 System and method for memory array decoding 有权
标题翻译：用于存储器阵列解码的系统和方法
公开(公告)号：US08203902B2
公开(公告)日：2012-06-19
申请号：US13214543
申请日：2011-08-22
申请人： Pantas Sutardja , Winston Lee
发明人： Pantas Sutardja , Winston Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C8/14 , G11C2207/2209
摘要： A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line.
摘要翻译：包括存储器阵列和读写/模块的存储器系统。存储器包括多个位线，多个字线和多个存储器单元，其中每个存储器单元形成在存储器阵列中位线和字线的相应交叉点处。读/写模块被配置为在读操作或写操作期间控制存储器阵列中的至少两个存储单元的激活，其中由读/写模块激活的至少两个存储单元位于不同的字线以及存储器阵列中的不同的位线，并且其中耦合到所述多个位线中的相同位线的每个存储器单元被配置为基于所述位线的选择被写入或从其读取。

6. 发明授权

US07863709B1 Low base resistance bipolar junction transistor array 有权
标题翻译：低基极电阻双极结晶体管阵列
公开(公告)号：US07863709B1
公开(公告)日：2011-01-04
申请号：US12104254
申请日：2008-04-16
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L27/082
CPC分类号： H01L27/1026
摘要： Methods and apparatuses directed to low base resistance bipolar junction transistor (BJT) devices are described herein. A low base resistance BJT device may include a collector layer, a base layer formed on the collector layer, a plurality of isolation trench lines formed in the base layer and extending into the collector layer, and a plurality of polysilicon lines formed on the base layer parallel to and overlapping the plurality of isolation trench lines. The base layer may be N-doped or P-doped.
摘要翻译：本文描述了针对低基极电阻双极结型晶体管（BJT）器件的方法和装置。低电阻BJT器件可以包括集电极层，形成在集电极层上的基极层，形成在基极层中并延伸到集电极层中的多个隔离沟槽线，以及形成在基极层上的多个多晶硅线平行于并重叠多个隔离沟槽线。基层可以是N掺杂或P掺杂的。

7. 发明授权

US07690229B2 Station for alternate locks 失效
标题翻译：站替代锁
公开(公告)号：US07690229B2
公开(公告)日：2010-04-06
申请号：US11729424
申请日：2007-03-27
申请人： Winston Lee McKee
发明人： Winston Lee McKee
IPC分类号： E05B65/06
CPC分类号： E05B67/383 , E05B73/0005 , Y10S70/63 , Y10T70/413 , Y10T70/5319 , Y10T292/1025
摘要： Locking devices are provided that can be opened by alternate users with different keys. The devices generally include a lock slider anchored to an anchor tab through one or more link sliders. The sliders can be slidably mounted to a slide mount, such as, e.g., a slide shaft or slide slit in a housing. When the anchor tab, link slider and lock slider are all shackled together with, e.g., two or more padlocks, the lock bolt of the lock slider is substantially immobilized with the device in a locked configuration. When one or more of the shackles is removed, the lock slider is free to moved to an unlocked position along the slide mount.
摘要翻译：提供了可以由具有不同键的备用用户打开的锁定设备。这些装置通常包括通过一个或多个连杆滑块锚定到锚定片的锁定滑块。滑块可以可滑动地安装到滑动安装件，例如滑动轴或者在壳体中的滑动狭缝。当锚定片，连杆滑块和锁定滑块都与例如两个或更多个挂锁一起被钩住时，锁定滑块的锁定螺栓基本上被固定在设备处于锁定构型中。当卸下一个或多个钩环时，锁定滑块可自由移动到沿着滑座的解锁位置。

8. 发明授权

US07571287B2 Multiport memory architecture, devices and systems including the same, and methods of using the same 有权
标题翻译：多端口存储器架构，包括相同的器件和系统以及使用它们的方法
公开(公告)号：US07571287B2
公开(公告)日：2009-08-04
申请号：US10702744
申请日：2003-11-05
申请人： Winston Lee , Sehat Sutardja , Donald Pannell
发明人： Winston Lee , Sehat Sutardja , Donald Pannell
IPC分类号： G06F12/00
CPC分类号： G11C7/1075
摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
摘要翻译：多端口内存架构，系统包括相同以及使用方法。架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。系统通常包括体现本文公开的一个或多个发明构思的系统。所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用消除FIFO。本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。

9. 发明授权

US06992165B2 Method for making amine-terminated polyarylene polyethers 失效
标题翻译：制备胺封端聚亚芳基聚醚的方法
公开(公告)号：US06992165B2
公开(公告)日：2006-01-31
申请号：US10740095
申请日：2003-12-17
申请人： Winston Lee Hedges
发明人： Winston Lee Hedges
IPC分类号： C08G75/00
CPC分类号： C08G65/4093
摘要： A method for making an amine-terminated polyarylene polyether thermoplastic in which a liquid/solid slurry reaction mixture is formed in an oxygen-free atmosphere. The reaction mixture is composed of a dihydroxyaromatic compound, a dihaloaromatic compound, an amino-hydroxyaromatic compound, a weak base, an aprotic polar solvent and a non-aromatic azeotrope former which is substantially imiscible with the aprotic polar solvent, said azeotrope former consisting of a molecule which has from 6 to 10 carbon atoms. The reaction mixture is refluxed at an elevated temperature to eventually produce a solution of the amine-terminated polyarylene polyether in the polar solvent. The method is designed for use in producing large amounts of thermoplastic in a simple, efficient and reliable manner.
摘要翻译：一种制备其中在无氧气氛中形成液体/固体淤浆反应混合物的胺封端聚亚芳基聚醚热塑性塑料的方法。该反应混合物由二卤代芳族化合物，氨基羟基芳族化合物，弱碱，非质子极性溶剂和与非质子极性溶剂基本上可混溶的非芳族共沸物组成，所述共沸物由具有6至10个碳原子的分子。将反应混合物在升高的温度下回流以最终产生胺封端的聚亚芳基聚醚在极性溶剂中的溶液。该方法设计用于以简单，有效和可靠的方式生产大量的热塑性塑料。

10. 发明申请

US20050001208A1 Hoist method and apparatus 审中-公开
标题翻译：起重机方法及装置
公开(公告)号：US20050001208A1
公开(公告)日：2005-01-06
申请号：US10833937
申请日：2004-04-28
申请人： Winston Lee
发明人： Winston Lee
IPC分类号： B66F3/08 , B66F1/00
CPC分类号： B66F3/08
摘要： The present invention features a hoist comprising a primary extension having a circular arrangement and that is helical in shape, or that is formed in the shape of a helix having several coils or laterals. The hoist further comprises a series of supports that comprise a pre-determined length and that dictates the height or extension distance to which the primary extension can extend. The supports are also comprised of a helical shape to allow the laterals of the primary extension to travel thereon once being formed together. Essentially, the primary extension is caused to extend and collapse by rotating the supports in the appropriate direction.
摘要翻译：本发明的特征在于一种起重机，其包括具有圆形布置并且呈螺旋形的主要延伸部，或者形成为具有多个线圈或侧面的螺旋形状的起重机。起重机还包括一系列支撑件，其包括预定长度并且指示主延伸部能够延伸的高度或延伸距离。支撑件还包括螺旋形状，以便一旦形成在一起就允许主延伸件的侧面行进。基本上，通过沿着适当的方向旋转支撑件，导致主要的延伸延伸和塌缩。

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