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31. 发明授权

US09520436B2 Solid-state imaging device and manufacturing method thereof 有权
标题翻译：固态成像装置及其制造方法
公开(公告)号：US09520436B2
公开(公告)日：2016-12-13
申请号：US15069542
申请日：2016-03-14
申请人： SEIKO EPSON CORPORATION
发明人： Kazunobu Kuwazawa , Noriyuki Nakamura , Mitsuo Sekisawa , Takehiro Endo
IPC分类号： H01L27/146 , H01L21/265 , H01L31/112 , H04N5/335 , H01L29/36 , H01L21/266
CPC分类号： H01L27/14643 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L27/14601 , H01L27/14603 , H01L27/14607 , H01L27/1461 , H01L27/14612 , H01L27/14614 , H01L27/14616 , H01L27/14689 , H01L29/36 , H04N5/335
摘要： A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P−-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N−-type impurity region that is located in the semiconductor layer under the P−-type impurity region and includes a portion that is under the pinning layer, and an N−-type impurity region that is in contact with the gate insulating film and the P−-type impurity region and is located so as to surround the N−-type impurity region in plan view.
摘要翻译：固态成像装置包括P阱，栅极绝缘膜，栅电极，P +型钉扎层，其位于P阱中，以便在栅电极之外并从第一端部开始位于P阱中的P型杂质区域，以从第一端部侧在栅电极下方延伸并与钉扎层接触，形成N型杂质区域其位于P型杂质区域下方的半导体层中，并且包括位于钉扎层下方的部分和与栅极绝缘膜和P型杂质接触的N型杂质区域并且在平面图中被定位成围绕N型杂质区域。

32. 发明申请

US20160351744A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160351744A1
公开(公告)日：2016-12-01
申请号：US15106996
申请日：2014-12-22
申请人： CANON KABUSHIKI KAISHA
发明人： Ryota Sekiguchi , Toshihiko Ouchi
IPC分类号： H01L31/112 , H01L31/108 , G01J1/44 , H01L27/146
CPC分类号： H01L31/1123 , G01J1/44 , G01J2001/4446 , G01N21/3581 , H01L27/0629 , H01L27/1463 , H01L27/14649 , H01L27/14689 , H01L29/66143 , H01L29/872 , H01L31/1085 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A semiconductor device includes a silicon substrate and a detection element and p-type and n-type MOS transistors, which are arranged on the silicon substrate, wherein the detection element includes a semiconductor layer, electrodes, and a Schottkey barrier disposed therebetween, the semiconductor layer is arranged just above a layer having the same composition and height as those of an impurity diffusion layer in the source or drain of the p-type or n-type MOS transistor, a region, in the silicon substrate, having the same composition and height as those of a channel region, in the silicon substrate, just below a gate oxide film of the p-type MOS transistor or the n-type MOS transistor, or a region, in the silicon substrate, having the same composition and height as those of a region just below a field oxide film disposed between the p-type and the n-type MOS transistor.
摘要翻译：半导体器件包括硅衬底和布置在硅衬底上的检测元件和p型和n型MOS晶体管，其中检测元件包括半导体层，电极和设置在其间的肖特基势垒，半导体层位于具有与p型或n型MOS晶体管的源极或漏极中的杂质扩散层相同的组成和高度的层的正上方，硅衬底中具有相同组成的区域，以及在硅衬底中刚好在p型MOS晶体管或n型MOS晶体管的栅极氧化膜的下方的沟道区的高度，或硅衬底中的具有相同组成和高度的区域位于p型和n型MOS晶体管之间的场氧化物膜正下方的区域。

33. 发明授权

US09508764B2 Monolithically integrated antenna and receiver circuit 有权
标题翻译：单片集成天线和接收器电路
公开(公告)号：US09508764B2
公开(公告)日：2016-11-29
申请号：US14122897
申请日：2012-05-31
申请人： Sebastian Boppel , Alvydas Lisauskas , Hartmut Roskos , Viktor Krozer
发明人： Sebastian Boppel , Alvydas Lisauskas , Hartmut Roskos , Viktor Krozer
IPC分类号： H01L27/146 , H01L31/101 , H01L31/112
CPC分类号： H01L27/14601 , H01L31/101 , H01L31/112
摘要： The invention relates to a device for detecting electromagnetic radiation in the THz frequency range, comprising at least one transistor (FET1, FET2), which has a first electrode, a second electrode, a control electrode, and a channel between the first electrode and the second electrode, and comprising an antenna structure. An electrode is connected to the antenna structure such that an electromagnetic signal which lies in the THz-frequency range and which is received by the antenna structure (1) can be fed into the channel between electrodes and the control electrode is connected to an electrode via a capacitor and/or the control electrode and the first electrode or the control electrode and the second electrode have an intrinsic capacitor such that no AC voltage drop occurs between the control electrode and the first electrode or the second electrode.
摘要翻译：本发明涉及一种用于检测太赫兹频率范围内的电磁辐射的装置，包括至少一个晶体管（FET1，FET2），其具有第一电极，第二电极，控制电极和第一电极与第二电极之间的通道第二电极，并且包括天线结构。电极连接到天线结构，使得位于太赫兹频率范围内且由天线结构（1）接收的电磁信号可以馈送到电极之间的通道中，并且控制电极通过电容器和/或控制电极以及第一电极或控制电极和第二电极具有本征电容器，使得控制电极和第一电极或第二电极之间不会发生交流电压降。

34. 发明授权

US09490283B2 Active pixel sensor with nanowire structured photodetectors 有权
标题翻译：有源像素传感器与纳米线结构光电探测器
公开(公告)号：US09490283B2
公开(公告)日：2016-11-08
申请号：US14293164
申请日：2014-06-02
申请人： ZENA TECHNOLOGIES, INC.
发明人： Young-June Yu , Munib Wober
IPC分类号： H01L29/15 , H01L27/146 , H01L31/0232 , H01L31/0352 , H01L31/101 , H01L31/102 , H01L31/112
CPC分类号： H01L27/14612 , H01L27/1461 , H01L27/14625 , H01L27/14643 , H01L27/14645 , H01L31/0232 , H01L31/02327 , H01L31/0352 , H01L31/035227 , H01L31/03529 , H01L31/101 , H01L31/102 , H01L31/1126 , Y02E10/50
摘要： An imaging device formed as an active pixel array combining a CMOS fabrication process and a nanowire fabrication process. The pixels in the array may include a single or multiple photogates surrounding the nanowire. The photogates control the potential profile in the nanowire, allowing accumulation of photo-generated charges in the nanowire and transfer of the charges for signal readout. Each pixel may include a readout circuit which may include a reset transistor, charge transfer switch transistor, source follower amplifier, and pixel select transistor. A nanowire is generally structured as a vertical rod on the bulk semiconductor substrate to receive light energy impinging onto the tip of the nanowire. The nanowire may be configured to function as either a photodetector or a waveguide configured to guild the light to the substrate. Light of different wavelengths can be detected using the imaging device.
摘要翻译：一种形成为组合CMOS制造工艺和纳米线制造工艺的有源像素阵列的成像器件。阵列中的像素可以包括围绕纳米线的单个或多个摄像机。摄影门控制纳米线中的电位分布，允许在纳米线中积累光生电荷并传输电荷用于信号读出。每个像素可以包括读出电路，其可以包括复位晶体管，电荷转移开关晶体管，源极跟随放大器和像素选择晶体管。纳米线通常构造为在体半导体衬底上的垂直杆，以接收入射到纳米线尖端的光能。纳米线可以被配置为用作被配置为将光引导到衬底的光电检测器或波导。可以使用成像装置检测不同波长的光。

35. 发明授权

US09318419B2 Conductive line structures and methods of forming the same 有权
标题翻译：导电线结构及其形成方法
公开(公告)号：US09318419B2
公开(公告)日：2016-04-19
申请号：US14532484
申请日：2014-11-04
申请人： Samsung Electronics Co., Ltd.
发明人： Sok-Won Lee , Joon-Hee Lee , Jung-Dal Choi , Seong-Min Jo
IPC分类号： H01L29/80 , H01L31/112 , H01L23/482 , H01L23/52 , H01L21/768 , H01L21/033 , H01L21/3213 , H01L21/764 , H01L27/115 , H01L23/522 , H01L23/532 , H01L23/528
CPC分类号： H01L23/4821 , H01L21/0337 , H01L21/32139 , H01L21/764 , H01L21/768 , H01L21/7682 , H01L21/76837 , H01L21/76838 , H01L21/76885 , H01L21/76895 , H01L23/4827 , H01L23/52 , H01L23/5222 , H01L23/528 , H01L23/53295 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L2924/0002 , H01L2924/00
摘要： Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.
摘要翻译：导电线结构及其形成方法包括第一和第二图案结构，绝缘层图案和绝缘夹层。第一图案结构包括导线图案和硬掩模，并且沿第一方向延伸。第二图案结构包括第二导电线图案和另一个硬掩模，并且图案结构的至少一部分沿第一方向延伸。绝缘层图案接触图形结构的端部。第一图案结构和绝缘层图案在平面图中形成闭合曲线形状，并且第二图案结构和另一绝缘层图案在平面图中形成另一封闭曲线形状。绝缘中间层覆盖图案结构的上部和绝缘层图案，图案结构之间的空气间隙和绝缘层图案之间的另一气隙。

36. 发明申请

US20160079465A1 PHOTO CELL DEVICES FOR PHASE-SENSITIVE DETECTION OF LIGHT SIGNALS 审中-公开
公开(公告)号：US20160079465A1
公开(公告)日：2016-03-17
申请号：US14880680
申请日：2015-10-12
申请人： Infineon Technologies AG
发明人： Thoralf Kautzsch
IPC分类号： H01L31/18 , H01L31/112
CPC分类号： H01L31/18 , G01S7/4861 , H01L31/02024 , H01L31/03529 , H01L31/103 , H01L31/112 , Y02E10/50
摘要： Embodiments relate to photo cell devices. In one embodiment, a trench-based photo cells provides very fast capture of photo-generated charge carriers, particularly when compared with conventional approaches, as the trenches of the photo cells create depleted regions deep within the bulk of the substrate that avoid the time-consuming diffusion of carriers.

37. 发明授权

US09202934B2 Junction field effect transistor, and method of manufacture thereof 有权
标题翻译：结型场效应晶体管及其制造方法
公开(公告)号：US09202934B2
公开(公告)日：2015-12-01
申请号：US14055738
申请日：2013-10-16
申请人： ANALOG DEVICES GLOBAL
发明人： Edward John Coyne
IPC分类号： H01L29/80 , H01L31/112 , H01L29/808 , H01L29/66 , H01L29/08 , H01L29/10
CPC分类号： H01L29/808 , H01L29/0843 , H01L29/1058 , H01L29/66893 , H01L29/66901
摘要： A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.
摘要翻译：一种形成结型场效应晶体管的方法，所述晶体管包括：背栅极; 一个渠道顶门电流与通道的漏极和源极; 其中所述方法包括选择所述顶栅极和所述后栅极之间的第一沟道尺寸，使得所述沟道中的有效电流流动路径发生在相对低的电场强度的区域中。

38. 发明授权

US09123873B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US09123873B2
公开(公告)日：2015-09-01
申请号：US14090487
申请日：2013-11-26
申请人： Samsung Display Co., Ltd.
发明人： Jeong Min Park , Ji-Hyun Kim , Jung-Soo Lee , Sung Kyun Park
IPC分类号： H01L31/112 , H01L33/58 , G02F1/1345 , G02F1/1362
CPC分类号： H01L27/124 , G02F1/13458 , G02F1/136227 , G02F1/1368 , H01L27/1248 , H01L29/78669 , H01L29/78678 , H01L33/58
摘要： Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating layer, the first passivation layer, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads.
摘要翻译：代替在非图像形成周边区域（PA）和薄膜晶体管阵列面板的图像形成显示区域中以相同的方式形成接触孔，DA中的接触孔形成为显着小于PA中的接触孔从而提高对应的显示装置的开口率。在一个示例性实施例中，在DA中不蚀刻无机栅极绝缘层，并且仅在位于DA中的无机绝缘层中只有无机第一钝化层被蚀刻以允许漏电极和相应的场产生电极之间的连通。另一方面，在外围区域中，同时蚀刻位于栅极线上的多个无机绝缘层，例如栅极绝缘层，第一钝化层和第二钝化层以及数据线，形成第二接触孔，第三接触孔接触孔暴露各个栅极焊盘和数据焊盘。

39. 发明授权

US09030189B2 Quantum dot photo-field-effect transistor 有权
标题翻译：量子点光场效应晶体管
公开(公告)号：US09030189B2
公开(公告)日：2015-05-12
申请号：US13596968
申请日：2012-08-28
申请人： Edward Hartley Sargent
发明人： Edward Hartley Sargent
IPC分类号： G01R31/00 , H01L31/0352 , H01L31/112
CPC分类号： H01L31/035218 , G01R31/2601 , H01L31/1129
摘要： Photo-field-effect transistor devices and associated methods are disclosed in which a photogate, consisting of a quantum dot sensitizing layer, transfers photoelectrons to a semiconductor channel across a charge-separating (type-II) heterointerface, producing a sustained primary and secondary flow of carriers between source and drain electrodes. The light-absorbing photogate thus modulates the flow of current along the channel, forming a photo-field effect transistor.
摘要翻译：公开了光场效应晶体管器件和相关方法，其中由量子点敏化层组成的光栅将光电子传送到跨越电荷分离（II型）异质界面的半导体通道，产生持续的一次和二次流源极和漏极之间的载流子。因此，光吸收光栅调制沿通道的电流流动，形成光场效应晶体管。

40. 发明授权

US09018769B2 Non-lithographic formation of three-dimensional conductive elements 有权
标题翻译：三维导电元件的非平版印刷形成
公开(公告)号：US09018769B2
公开(公告)日：2015-04-28
申请号：US14243484
申请日：2014-04-02
申请人： Tessera, Inc.
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L29/80 , H01L31/112 , H01L29/00 , H01L23/522 , H01L21/768 , H01L23/00 , H01L23/498
CPC分类号： H01L21/76879 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L23/4985 , H01L23/5226 , H01L24/06 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
摘要翻译：提供了在基板上形成导电元件的方法和所得到的组件。该方法包括在覆盖设置在基板上的电介质区域上的牺牲层中形成凹槽。槽优选地沿着衬底的倾斜表面延伸。牺牲层优选通过非光刻方法去除，例如用激光烧蚀，机械研磨或喷砂。在沟槽中形成导电元件。可以形成凹槽。凹槽和导电元件可以沿着衬底的任何表面形成，包括在其中形成的沟槽和通孔内，并且可以连接到衬底的前表面和/或后表面上的导电焊盘。导电元件优选通过电镀形成，并且可以或可以不与基板的表面一致。

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