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41. 发明授权

US08096705B2 Method and system for real-time estimation and prediction of the thermal state of a microprocessor unit 有权
标题翻译：用于实时估计和预测微处理器单元的热状态的方法和系统
公开(公告)号：US08096705B2
公开(公告)日：2012-01-17
申请号：US12756733
申请日：2010-04-08
申请人： Sri M. Sri-Jayantha , Hien P. Dang , Arun Sharma
发明人： Sri M. Sri-Jayantha , Hien P. Dang , Arun Sharma
IPC分类号： G01K7/00 , G01K3/00 , G01N25/00
CPC分类号： G06F1/206
摘要： A method of estimating temperature of a transient nature of a thermal system, including, without a temperature measurement being made available, determining a drive current and thermal parameters of the thermal system.
摘要翻译：一种估计热系统的瞬态特性的温度的方法，包括在没有提供温度测量的情况下确定热系统的驱动电流和热参数。

42. 发明授权

US08085234B2 Capacitive load driving circuit, method of driving capacitive load, method of driving liquid crystal display device 有权
标题翻译：电容负载驱动电路，驱动电容性负载的方法，驱动液晶显示装置的方法
公开(公告)号：US08085234B2
公开(公告)日：2011-12-27
申请号：US11984036
申请日：2007-11-13
申请人： Kouichi Nishimura , Takashi Nose
发明人： Kouichi Nishimura , Takashi Nose
IPC分类号： G09G3/36
CPC分类号： H03K17/122 , G09G3/2011 , G09G3/3688 , G09G2310/02 , G09G2310/027 , G09G2310/0289 , G09G2310/066
摘要： A capacitive load driving circuit includes a gate driver, and a source driver. The gate driver drives a plurality of capacitive loads arranged in a matrix form in a row direction. The source driver drives the plurality of capacitive loads in a column direction. The source driver includes a plurality of output circuits configured to be arranged in a row direction. Each of the plurality of output circuits changes a slew rate based on a column position of a capacitive load of the plurality of capacitive loads driven by the gate driver.
摘要翻译：电容性负载驱动电路包括栅极驱动器和源极驱动器。栅极驱动器以行方向驱动以矩阵形式布置的多个电容性负载。源极驱动器在列方向驱动多个容性负载。源极驱动器包括配置为沿行方向布置的多个输出电路。多个输出电路中的每一个基于由栅极驱动器驱动的多个容性负载的容性负载的列位置来改变压摆率。

43. 发明授权

US08078778B2 Image processing apparatus for reading compressed data from and writing to memory via data bus and image processing method 有权
标题翻译：用于经由数据总线读取压缩数据并写入存储器的图像处理装置和图像处理方法
公开(公告)号：US08078778B2
公开(公告)日：2011-12-13
申请号：US12081091
申请日：2008-04-10
申请人： Kazuhiro Fuji
发明人： Kazuhiro Fuji
IPC分类号： G06F13/00 , G06F15/16
CPC分类号： H04N19/00 , H04N19/42
摘要： An image processing apparatus includes a data bus provided to access a memory, a compressing unit which compresses an image data and outputs a compressed image data, a write unit which writes the compressed image data into the memory via the data bus, a read unit which reads a compressed image from the memory via the data bus, a decompression unit which decompresses the compressed data read by the read unit, and a control unit which controls operations of the write unit and the read unit, based on an amount per unit time of the compressed image data outputted from the compressing unit, an amount per unit time of the compressed image data read from the memory and a degree of congestion of the data bus.
摘要翻译：图像处理装置包括：提供用于访问存储器的数据总线;压缩单元，压缩图像数据并输出压缩图像数据;写入单元，其经由数据总线将压缩图像数据写入存储器;读取单元，经由数据总线从存储器读取压缩图像，解压缩由读取单元读取的压缩数据的解压缩单元，以及控制单元，其基于每单位时间的量来控制写入单元和读取单元的操作从压缩单元输出的压缩图像数据，从存储器读取的压缩图像数据的每单位时间的量和数据总线的拥塞程度。

44. 发明授权

US08069338B2 Data processing device and control method for preventing an exception caused by an instruction sent to a peripheral device by a branch source program from occurring during execution of a branch destination program or interrupt program 有权
标题翻译：用于防止由分支源程序发送到外围设备的指令在执行分支目的地程序或中断程序期间发生的异常的数据处理设备和控制方法
公开(公告)号：US08069338B2
公开(公告)日：2011-11-29
申请号：US12292259
申请日：2008-11-14
申请人： Hitoshi Suzuki , Yukihiko Akaike
发明人： Hitoshi Suzuki , Yukihiko Akaike
IPC分类号： G06F9/32 , G06F15/16 , G06F9/48
CPC分类号： G06F9/3877 , G06F9/30054 , G06F9/30087 , G06F9/3836 , G06F9/3842 , G06F9/3861
摘要： A data processing device includes a program execution section to supply an operation direction signal to a peripheral device based on an executed program and execute a branch operation in response to a branch direction signal, and a branch wait operation section to receive the branch direction signal and a peripheral device status notification signal indicating whether an operation performed in the peripheral device is being executed. The branch wait operation section outputs an instruction issue stop signal directing waiting of the branch operation to the program execution section if the branch direction signal is input during a period when the peripheral device status notification signal is active indicating that the operation in the peripheral device is being executed.
摘要翻译：数据处理装置包括：程序执行部，其根据执行的程序向外围设备提供操作方向信号，并响应于分支方向信号执行分支操作;以及分支等待操作部分，用于接收分支方向信号，以及指示是否正在执行在外围设备中执行的操作的外围设备状态通知信号。如果在外围设备状态通知信号有效的期间输入了分支方向信号，则分支等待操作部分输出指示将分支操作等待到程序执行部分的指令发出停止信号，表示外围设备中的操作是被执行

45. 发明授权

US08055965B2 Semiconductor integrated circuit and method of testing the same 有权
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US08055965B2
公开(公告)日：2011-11-08
申请号：US12801182
申请日：2010-05-26
申请人： Naoki Kaneko
发明人： Naoki Kaneko
IPC分类号： G01R31/28
CPC分类号： G01R31/318575 , G01R31/318552 , G06F1/04 , G06F1/32
摘要： A semiconductor integrated circuit includes: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip-flops, respectively. The plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection. Each of the plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of the plurality of scan flip-flops based on the gating setting data.
摘要翻译：半导体集成电路包括：多个扫描触发器，被配置为在扫描测试中形成扫描链; 以及多个时钟选通电路，分别连接在时钟输入和多个扫描触发器的对应部分之间。多个时钟选通电路串联连接以形成一个链，并且选通设置数据通过链路连接串行输入。多个时钟门控电路中的每一个基于门控设置数据控制时钟输入与多个扫描触发器的相应部分之间的连接。

46. 发明授权

US08052523B2 Gaming system 有权
标题翻译：游戏系统
公开(公告)号：US08052523B2
公开(公告)日：2011-11-08
申请号：US11892383
申请日：2007-08-22
申请人： Yukinori Inamura
发明人： Yukinori Inamura
IPC分类号： A63F9/24 , A63F13/00
CPC分类号： G07F17/3258 , G07F17/3244
摘要： A gaming system comprising: a gaming machine and a server capable of communicating with the gaming machine is provided. The gaming machine comprises a receiving unit for receiving a game medium. The server comprises a plurality of first storage devices for storing a plurality of accumulated amounts to which predetermined proportions of bet game media received by the receiving unit is cumulatively added, a first lottery unit for conducting a lottery to determine whether or not one of the accumulated amounts is to be paid, and a first processor that operates to transmit an instruction for payout based on a result of the lottery and reset all accumulated amounts stored in the plurality of first storage devices when the instruction for payout is transmitted based on the result of the lottery.
摘要翻译：提供了一种游戏系统，包括：游戏机和能够与游戏机进行通信的服务器。游戏机包括用于接收游戏媒体的接收单元。服务器包括：多个第一存储装置，用于存储多个积累量，累积量由接收单元接收到预定比例的赌注游戏媒体;第一彩票单元，用于进行彩票，以确定是否累积将支付金额，以及第一处理器，其操作以基于彩票的结果发送用于支付的指示，并且当根据付款的结果发送支付指令时，存储在多个第一存储装置中的所有累积量彩票。

47. 发明授权

US08035365B2 DC converter which has switching control unit to select PWM signal or PFM signal 失效
标题翻译： DC转换器具有选择PWM信号或PFM信号的开关控制单元
公开(公告)号：US08035365B2
公开(公告)日：2011-10-11
申请号：US12320981
申请日：2009-02-10
申请人： Hidehiro Kikuchi
发明人： Hidehiro Kikuchi
IPC分类号： G05F1/00
CPC分类号： H02M3/156
摘要： A DC (direct current) converter includes a PWM (pulse width modulation) pulse generation unit outputting a PWM pulse signal whose duty ratio is controlled in accordance with an output voltage, a PFM (pulse frequency modulation) pulse generation unit outputting a PFM pulse signal whose pulse output interval is controlled in accordance with an output voltage, a selection circuit selecting and outputting any one of the PWM pulse signal and the PFM pulse signal in response to a selection signal, a drive circuit unit driving a load and generating an output voltage on the basis of a signal outputted from the selection circuit, and a switching control unit outputting the selection signal. When the selection signal is in a second state, the switching control unit detects a fact that the number of pulses of the PFM pulse signal in a measurement period increases to or above a set value of the maximum number of pulses, and switches the selection signal to a first state.
摘要翻译： DC（直流）转换器包括PWM（脉冲宽度调制）脉冲产生单元，输出根据输出电压控制占空比的PWM脉冲信号; PFM（脉冲频率调制）脉冲产生单元，输出PFM脉冲信号其脉冲输出间隔根据输出电压进行控制，选择电路响应于选择信号选择并输出PWM脉冲信号和PFM脉冲信号中的任何一个，驱动电路单元驱动负载并产生输出电压基于从选择电路输出的信号，以及切换控制单元输出选择信号。当选择信号处于第二状态时，切换控制单元检测在测量周期中PFM脉冲信号的脉冲数增加到或超过最大脉冲数的设定值的事实，并且切换选择信号到第一个状态。

48. 发明授权

US08023573B2 Wireless communication system, wireless communication device, and valid path detection method therefor 失效
标题翻译：无线通信系统，无线通信装置及其有效路径检测方法
公开(公告)号：US08023573B2
公开(公告)日：2011-09-20
申请号：US11979872
申请日：2007-11-09
申请人： Shingo Kikuchi
发明人： Shingo Kikuchi
IPC分类号： H04L27/00
CPC分类号： H04W56/0045 , H04B1/7117 , Y02D70/1262 , Y02D70/40
摘要： A wireless communication system according to an exemplary aspect of the present invention is a wireless communication system which performs wireless communications between a first wireless communication device and a second wireless communication device, wherein the first wireless communication device includes: a delay profile calculation unit for calculating a delay profile by calculating a correlation value for a received signal; a valid path detection unit for detecting a valid path using the delay profile and forcibly detecting a valid path when there is no path satisfying a condition of the valid path; and a forcible valid path notification unit for notifying that the valid path is forcibly detected.
摘要翻译：根据本发明的示例性方面的无线通信系统是执行第一无线通信设备和第二无线通信设备之间的无线通信的无线通信系统，其中所述第一无线通信设备包括：延迟分布计算单元，用于计算通过计算接收信号的相关值来确定延迟分布; 有效路径检测单元，用于当不存在满足有效路径的条件的路径时，使用所述延迟分布来检测有效路径并强制检测有效路径; 以及用于通知有效路径被强制检测的强制有效路径通知单元。

49. 发明授权

US07985686B2 Method of forming a nonvolatile memory device using semiconductor nanoparticles 有权
标题翻译：使用半导体纳米颗粒形成非易失性存储器件的方法
公开(公告)号：US07985686B2
公开(公告)日：2011-07-26
申请号：US11373127
申请日：2006-03-13
申请人： Charles T. Black , Kathryn Wilder Guarini
发明人： Charles T. Black , Kathryn Wilder Guarini
IPC分类号： H01L21/311 , H01L21/8247
CPC分类号： H01L29/66825 , B82Y10/00 , G11C2216/06 , H01L21/02118 , H01L21/02227 , H01L21/02532 , H01L21/02636 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L29/42332 , H01L29/7887 , H01L29/7923 , Y10S438/947 , Y10S977/78 , Y10S977/783 , Y10S977/813 , Y10S977/856 , Y10S977/883 , Y10S977/888 , Y10S977/893
摘要： A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.
摘要翻译：用于场效应晶体管的浮动栅极（及其形成方法和形成均匀的纳米颗粒阵列的方法）包括多个离散的纳米颗粒，其中纳米颗粒的尺寸，间距和密度中的至少一个是其中之一模板化并由自组装材料限定。

50. 发明授权

US07982490B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07982490B2
公开(公告)日：2011-07-19
申请号：US12382727
申请日：2009-03-23
申请人： Masashi Kurokawa , Kenichi Kawakami
发明人： Masashi Kurokawa , Kenichi Kawakami
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361 , H03K17/162
摘要： Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.
摘要翻译：提供了一种半导体集成电路，包括：连接在电源（VDD0）和地（GND0）之间的输出电路，具有连接到输入端子的输入，并且具有连接到输出端子的输出; 以及连接在输入端子和输出端子之间的电源噪声消除电路，以产生消除从电源（VDD0）流向输出端子的电流或从输出端子流向地的电流（ GND0），基于输入端子和输出端子之间的电位差。

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