专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US09117847B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09117847B2
公开(公告)日：2015-08-25
申请号：US14516592
申请日：2014-10-17
申请人： UNITED MICROELECTRONICS CORP.
发明人： Cheng-Yuan Hsu , Chi Ren , Tzeng-Fei Wen
IPC分类号： H01L21/06 , H01L29/66 , H01L29/423 , H01L29/788 , H01L21/28 , H01L27/115 , H01L21/266
CPC分类号： H01L29/66825 , H01L21/266 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/42332 , H01L29/6653 , H01L29/6656 , H01L29/7881 , H01L29/7882
摘要： A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer.
摘要翻译：公开了制造半导体器件的方法。该方法包括以下步骤：在半导体衬底上依次形成玛瑙电介质层和第一栅极层，其中栅介电层位于第一栅层和半导体衬底之间; 在所述第一栅极层中形成至少一个开口; 在所述半导体衬底上共形形成第一电介质层，其中所述第一电介质层覆盖所述第一栅极层; 以及形成填充所述开口并与所述第一栅极层重叠的第二栅极层。

42. 发明授权

US07623185B2 Synchronization control apparatus and method 有权
标题翻译：同步控制装置及方法
公开(公告)号：US07623185B2
公开(公告)日：2009-11-24
申请号：US11306195
申请日：2005-12-19
申请人： Ching-Tzong Wang , Szu-Ping Chen
发明人： Ching-Tzong Wang , Szu-Ping Chen
IPC分类号： H04N5/04 , H04N5/10
CPC分类号： G09G5/005 , G09G3/2096 , G09G2310/0224 , G09G2310/08 , G09G2340/0407
摘要： A synchronization control apparatus for driving a display module in an interlacing scan mode includes: a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal; and a multiplexer coupled to the delay circuit for selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal.
摘要翻译：用于以隔行扫描模式驱动显示模块的同步控制装置包括：用于延迟输入垂直同步（IVS）信号以产生延迟信号的延迟电路; 以及耦合到延迟电路的多路复用器，用于根据奇数/偶数场指示信号选择IVS信号和延迟信号中的一个，以产生输出垂直同步（OVS）信号。

43. 发明授权

US07436356B2 Method of cross-correlation and continuous wave interference suppression for GPS signal and associated GPS receiver 有权
标题翻译： GPS信号及相关GPS接收机的互相关和连续波干扰抑制方法
公开(公告)号：US07436356B2
公开(公告)日：2008-10-14
申请号：US11277363
申请日：2006-03-24
申请人： Andrey Bochkovskiy , Mikhail Goloubev , Sergey Pospelov , Mikhail Vasilyev , Valeri Tchistiakov , Mikhail Kholostov , Sergey Nozdrachev , Nikolay Mikhaylov , Bijan Jalali
发明人： Andrey Bochkovskiy , Mikhail Goloubev , Sergey Pospelov , Mikhail Vasilyev , Valeri Tchistiakov , Mikhail Kholostov , Sergey Nozdrachev , Nikolay Mikhaylov , Bijan Jalali
IPC分类号： G01S1/00 , G01S13/58 , G01S1/08 , H03D1/00
CPC分类号： G01S19/29 , G01S19/21
摘要： A method for processing weak indoor signals in presence of cross-correlation or continuous wave interference and associated GPS receiver are provided. The method comprises providing a two-dimensional delay-Doppler accumulated power pattern having a plurality of accumulated powers corresponding to frequency and time; for a predetermined frequency, determining an average value of accumulated powers of the two-dimensional delay-Doppler accumulated power pattern over a plurality of times; and subtracting the average value from the accumulated powers used in determining the average at the frequency over the plurality of times to generate a delay-Doppler accumulated power pattern with suppressed interference effect.
摘要翻译：提供了在存在互相关或连续波干扰的情况下处理弱室内信号的方法和相关联的GPS接收机。该方法包括提供具有对应于频率和时间的多个累加功率的二维延迟多普勒累积功率模式; 对于预定频率，多次确定二维延迟多普勒累积功率模式的累积功率的平均值; 以及从多次确定频率上的平均值所使用的累积功率中减去平均值，以产生具有抑制干扰效应的延迟多普勒累积功率模式。

44. 发明授权

US07397853B2 Adaptive de-blocking filtering apparatus and method for MPEG video decoder 有权
标题翻译：用于MPEG视频解码器的自适应去块滤波装置和方法
公开(公告)号：US07397853B2
公开(公告)日：2008-07-08
申请号：US10709338
申请日：2004-04-29
申请人： Do-Kyoung Kwon , Mei-Yin Shen , Chung-Chieh Kuo
发明人： Do-Kyoung Kwon , Mei-Yin Shen , Chung-Chieh Kuo
IPC分类号： H04B1/66 , H04N7/12
CPC分类号： H04N19/86 , H04N19/117 , H04N19/137 , H04N19/14 , H04N19/159 , H04N19/162 , H04N19/176 , H04N19/61
摘要： A post processing de-blocking filter includes a threshold determination unit for adaptively determining a plurality of threshold values according to at least differences in quantization parameters QPs of a plurality of adjacent blocks in a received video stream and to a user defined offset (UDO) allowing the threshold levels to be adjusted according to the UDO value; an interpolation unit for performing an interpolation operation to estimate pixel values in an interlaced field if the video stream comprises interlaced video; and a de-blocking filtering unit for determining a filtering range specifying a maximum number of pixels to filter around a block boundary between the adjacent blocks, determining a region mode according to local activity around the block boundary, selecting one of a plurality of at least three filters, and filtering a plurality of pixels around the block boundary according to the filtering range, the region mode, and the selected filter.
摘要翻译：后处理解块滤波器包括阈值确定单元，用于根据接收到的视频流中的多个相邻块的量化参数QP的至少差异自适应地确定多个阈值，并且允许用户定义的偏移（UDO）允许根据UDO值调整的阈值水平; 插值单元，用于如果所述视频流包括隔行扫描视频，则执行用于估计隔行扫描场中的像素值的内插操作; 以及解块滤波单元，用于确定指定最大数量的像素以过滤相邻块之间的块边界的滤波范围，根据块边界周围的局部活动确定区域模式，至少选择多个三个滤波器，并且根据滤波范围，区域模式和所选滤波器对块边界周围的多个像素进行滤波。

45. 发明授权

US07111107B2 Microcontroller with dedicated memory bank for servicing interrupts 有权
标题翻译：具有专用存储体的微控制器用于维修中断
公开(公告)号：US07111107B2
公开(公告)日：2006-09-19
申请号：US10707107
申请日：2003-11-20
申请人： Pao-Ching Tseng , Ping-Cheng Sung , Ping-Sheng Chen , Li-Chun Tu
发明人： Pao-Ching Tseng , Ping-Cheng Sung , Ping-Sheng Chen , Li-Chun Tu
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F12/0623
摘要： A microcontroller with expandable memory banks has a microprocessor, a plurality of memory banks with only one page for storing interrupt service routines(ISR), a memory bank control circuit connected to the microprocessor, and a multiplexer for connecting the microprocessor with the plurality of memory banks. The memory bank control circuit generates a selection signal according to an interrupt signal and a microprocessor interrupt service routine execution end signal. The multiplexer outputs a page selection signal from the microprocessor or outputs a predetermined page selection signal according to the output signal from the memory bank control circuit.
摘要翻译：具有可扩展存储体的微控制器具有微处理器，多个存储体仅具有一页用于存储中断服务程序（ISR），连接到微处理器的存储器组控制电路以及用于将微处理器与多个存储器连接的多路复用器银行。存储体控制电路根据中断信号和微处理器中断服务程序执行结束信号产生选择信号。复用器从微处理器输出页选择信号，或者根据来自存储体控制电路的输出信号输出预定页选择信号。

46. 发明授权

US07015839B1 Mapping method utilizing look-up table and related apparatus 有权
标题翻译：利用查找表和相关设备的映射方法
公开(公告)号：US07015839B1
公开(公告)日：2006-03-21
申请号：US10905492
申请日：2005-01-06
申请人： Hsien-Chun Chang , Jin-Sheng Gong
发明人： Hsien-Chun Chang , Jin-Sheng Gong
IPC分类号： H03M7/00
CPC分类号： H03M7/30
摘要： A method includes utilizing the look-up table to store a plurality of basic values and a plurality of delta value sets, wherein each of the delta value sets represents a difference between a corresponding basic value and another basic value adjacent to the corresponding basic value; determining a first basic value and a first delta value set according to an input value; and generating an output value according to the first basic value and the first delta value set.
摘要翻译：一种方法包括利用查找表来存储多个基本值和多个Δ值集合，其中Δ值集合中的每一个表示对应的基本值和与相应的基本值相邻的另一个基本值之间的差; 根据输入值确定第一基本值和第一增量值集合; 以及根据所述第一基本值和所述第一增量值集合生成输出值。

47. 发明授权

US06972606B2 Delay circuits and related apparatus for extending delay time by active feedback elements 有权
标题翻译：延迟电路和相关装置，用于通过主动反馈元件延长延迟时间
公开(公告)号：US06972606B2
公开(公告)日：2005-12-06
申请号：US10708104
申请日：2004-02-10
申请人： Wei-Ming Ku , Yu-Ming Hsu , Wei-Wu Liao
发明人： Wei-Ming Ku , Yu-Ming Hsu , Wei-Wu Liao
IPC分类号： G11C7/12 , H03H11/26 , H03K5/00 , H03K5/08 , H03K5/13
CPC分类号： H03K5/13 , H03K5/082 , H03K2005/00156 , H03K2005/00195
摘要： A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator, a voltage generator for providing a reference voltage, a differential amplifier, and a feedback control module. The current generator starts to provide a charging current to the storage unit when the input signal changes level, such that an output charging voltage of the storages unit is gradually charged to reach the reference voltage. The feedback control module is capable of dynamically decreasing the charging current provided to the storage unit as the charging voltage is approaching the reference voltage, and the amplifier will change the level of the output voltage when the charging voltage reaches the reference voltage.
摘要翻译：一种用于提供更长延迟时间的延迟电路和相关装置，使得当输入信号的电平改变时，在预定延迟时间之后，输出信号的电平相应地改变。延迟电路具有存储单元，电流发生器，用于提供参考电压的电压发生器，差分放大器和反馈控制模块。当输入信号改变电平时，电流发生器开始向存储单元提供充电电流，使得存储单元的输出充电电压逐渐被充电以达到参考电压。当充电电压接近参考电压时，反馈控制模块能够动态地减小提供给存储单元的充电电流，并且当充电电压达到参考电压时，放大器将改变输出电压的电平。

48. 发明授权

US06855598B2 Flash memory cell including two floating gates and an erasing gate 有权
标题翻译：闪存单元包括两个浮动栅极和一个擦除栅极
公开(公告)号：US06855598B2
公开(公告)日：2005-02-15
申请号：US10249059
申请日：2003-03-13
申请人： Chih-Wei Hung , Cheng-Yuan Hsu , Da Sung , Chien-Chih Du
发明人： Chih-Wei Hung , Cheng-Yuan Hsu , Da Sung , Chien-Chih Du
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory includes a substrate, at least a source and two drains formed in the substrate, and the source located between the drains, two tunnel oxide layers formed on the substrate between each drain and the source, a floating gate formed on each of the tunnel oxide layers, a plurality of first oxide layers formed aside each of the floating gates, a dielectric layer formed on each of the floating gates, a control gate formed on each of the dielectric layers, a plurality of second oxide layers formed on surfaces of the control gates and extending toward both sides of the control gates, a lateral width of each second oxide layer being larger than a lateral width of each oxide layer, a third oxide layer formed on the source, and an erasing gate formed on the third oxide layer and located between the floating gates.
摘要翻译：闪速存储器包括衬底，至少形成在衬底中的源极和两个漏极，以及位于漏极之间的源极，在每个漏极和源极之间在衬底上形成的两个隧道氧化物层，在每个漏极和源极之间形成的浮动栅极隧道氧化物层，在每个浮置栅极上形成的多个第一氧化物层，形成在每个浮置栅极上的电介质层，形成在每个电介质层上的控制栅极，多个第二氧化物层，控制栅极并且朝向控制栅极的两侧延伸，每个第二氧化物层的横向宽度大于每个氧化物层的横向宽度，形成在源极上的第三氧化物层，以及形成在第三氧化物上的擦除栅极层和位于浮动门之间。

49. 发明授权

US06842374B2 Method for operating N-channel electrically erasable programmable logic device 有权
标题翻译：用于操作N沟道电可擦除可编程逻辑器件的方法
公开(公告)号：US06842374B2
公开(公告)日：2005-01-11
申请号：US10248283
申请日：2003-01-06
申请人： Kung-Hong Lee , Ching-Hsiang Hsu , Ya-Chin King , Shih-Jye Shen , Ming-Chou Ho
发明人： Kung-Hong Lee , Ching-Hsiang Hsu , Ya-Chin King , Shih-Jye Shen , Ming-Chou Ho
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11558 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate. By Applying a sufficient voltage on the first N-type doped region (VBL), and changing a select gate voltage (VSG) or the third N-type doped region voltage (VSL) applied on the second gate of the EEPLD, the operation of the EEPLD can be selectively implemented either under a channel hot hole (CHH) program mode or a channel hot electron (CHE) erase mode.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包含P型衬底。第一N型掺杂区域设置在P型衬底中。用于存储数据的第一栅极覆盖P型衬底并与第一N型掺杂区域相邻。第二N型掺杂区域横向设置在P型衬底中。第二N型掺杂区域也与第一栅极相邻。作为EEPLD的选择栅极或选择栅极的第二栅极覆盖P型衬底并与第二N型掺杂区域相邻。在P型衬底中设置第三N型掺杂区域。第三N型掺杂区域与第二栅极相邻。通过在第一N型掺杂区域（VBL）上施加足够的电压，并且改变施加在EEPLD的第二栅极上的选择栅极电压（VSG）或第三N型掺杂区域电压（VSL），操作可以在通道热孔（CHH）编程模式或通道热电子（CHE）擦除模式）下选择性地实施EEPLD。

50. 发明授权

US11270442B2 Motion image integration method and motion image integration system capable of merging motion object images 有权
公开(公告)号：US11270442B2
公开(公告)日：2022-03-08
申请号：US16745258
申请日：2020-01-16
申请人： Realtek Semiconductor Corp.
发明人： Chao-Hsun Yang , Shang-Lun Chan , Chun-Chang Wu , Shih-Tse Chen
IPC分类号： G06T7/215 , G06T7/246
摘要： A motion image integration method includes acquiring a raw image, detecting a first motion region image and a second motion region image by using a motion detector according to the raw image, merging the first motion region image with the second motion region image for generating a motion object image according to a relative position between the first motion region image and the second motion region image, and cropping the raw image to generate a sub-image corresponding to the motion object image according to the motion object image. A range of the motion object image is greater than or equal to a total range of the first motion region image and the second motion region image. Shapes of the first motion region image, the second motion region image, and the motion object image are polygonal shapes.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式