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1. 发明申请

US20190172834A1 SINGLE POLY NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND SINGLE POLY NON-VOLATILE MEMORY DEVICE ARRAY 审中-公开
公开(公告)号：US20190172834A1
公开(公告)日：2019-06-06
申请号：US16256137
申请日：2019-01-24
申请人： MagnaChip Semiconductor, Ltd.
发明人： Su Jin KIM , Hye Jin YOO
IPC分类号： H01L27/11558 , H01L29/66 , G11C16/14 , G11C16/10 , H01L29/10 , H01L29/08 , H01L29/788 , H01L27/11524 , G11C16/04
CPC分类号： H01L27/11558 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/14 , G11C2216/10 , H01L27/11524 , H01L29/0847 , H01L29/1095 , H01L29/66825 , H01L29/7883
摘要： A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

2. 发明授权

US10020268B2 Random number generator device and control method thereof 有权
公开(公告)号：US10020268B2
公开(公告)日：2018-07-10
申请号：US15486310
申请日：2017-04-13
申请人： eMemory Technology Inc.
发明人： Wei-Zhe Wong , Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： G11C17/00 , H01L23/00 , H01L23/522 , H01L27/088 , H01L29/06 , G11C16/14 , H01L27/11507 , H01L27/11529 , H01L29/423 , G06F7/58 , G11C17/16 , G11C17/18 , G11C16/04 , H01L27/11558 , H01L29/78
CPC分类号： H01L23/573 , G06F7/588 , G11C16/0441 , G11C16/14 , G11C17/16 , G11C17/18 , G11C2216/10 , H01L23/5226 , H01L27/0883 , H01L27/11507 , H01L27/11529 , H01L27/11558 , H01L28/00 , H01L29/0653 , H01L29/42328 , H01L29/42344 , H01L29/42352 , H01L29/7831 , H01L29/7833 , H01L29/7841
摘要： A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

3. 发明申请

US20170178734A1 DEVICE FOR GENERATING A VOLTAGE REFERENCE COMPRISING A NON-VOLATILE MEMORY CELL 有权
公开(公告)号：US20170178734A1
公开(公告)日：2017-06-22
申请号：US15244664
申请日：2016-08-23
申请人： STMicroelectronics S.r.l , STMicroelectronics Design & Application S.R.O.
发明人： Marco Pasotti , Fabio De Santis , Roberto Bregoli , Dario Livornesi , Sandor Petenyi
IPC分类号： G11C16/30 , G11C5/14 , G11C16/04 , H01L27/115 , G11C16/28
CPC分类号： G11C16/30 , G05F3/30 , G11C5/147 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/28 , G11C2216/10 , H01L27/11521 , H01L27/1156 , H03F3/45188 , H03F3/45475 , H03F2200/456 , H03F2203/45341 , H03F2203/45342 , H03F2203/45528 , H03F2203/45674 , H03F2203/45676
摘要： A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

4. 发明授权

US09666279B2 Non-volatile memory for high rewrite cycles application 有权
公开(公告)号：US09666279B2
公开(公告)日：2017-05-30
申请号：US15193103
申请日：2016-06-26
申请人： eMemory Technology Inc.
发明人： Wen-Hao Ching , Yen-Hsin Lai , Shih-Chen Wang
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788 , H01L27/11558 , H01L29/51 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L29/06 , H01L29/423 , G11C16/10 , G11C16/24 , H01L27/11524 , G11C16/34 , G11C16/14 , G11C16/26 , H01L29/45
CPC分类号： G11C16/0433 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C2216/10 , H01L27/11524 , H01L27/11558 , H01L27/1157 , H01L29/0649 , H01L29/42328 , H01L29/42344 , H01L29/45 , H01L29/512 , H01L29/66545 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/7882 , H01L29/792
摘要： A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

5. 发明授权

US09425204B2 Non-volatile memory for high rewrite cycles application 有权
公开(公告)号：US09425204B2
公开(公告)日：2016-08-23
申请号：US14271429
申请日：2014-05-06
申请人： eMemory Technology Inc.
发明人： Wen-Hao Ching , Yen-Hsin Lai , Shih-Chen Wang
IPC分类号： H01L27/115 , G11C16/04 , H01L29/788 , H01L29/51 , H01L29/66 , H01L29/792 , H01L29/06 , H01L29/423 , G11C16/10 , G11C16/24 , G11C16/34 , G11C16/14 , G11C16/26 , H01L29/45
CPC分类号： G11C16/0433 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C2216/10 , H01L27/11524 , H01L27/11558 , H01L27/1157 , H01L29/0649 , H01L29/42328 , H01L29/42344 , H01L29/45 , H01L29/512 , H01L29/66545 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/7882 , H01L29/792
摘要： A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

6. 发明授权

US09373396B2 Side wall bit line structures 有权
标题翻译：侧壁位线结构
公开(公告)号：US09373396B2
公开(公告)日：2016-06-21
申请号：US14716382
申请日：2015-05-19
申请人： SANDISK 3D LLC
发明人： Perumal Ratnam , Christopher Petti , Tianhong Yan
IPC分类号： H01L29/02 , G11C13/00 , G06F11/10 , H01L27/24 , H01L29/786 , H01L45/00 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C7/12 , G11C7/18 , G11C29/02 , G11C29/12
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

7. 发明授权

US09298653B2 Serial-parallel interface circuit with nonvolatile memory 有权
标题翻译：具有非易失性存储器的串行 - 并行接口电路
公开(公告)号：US09298653B2
公开(公告)日：2016-03-29
申请号：US14166869
申请日：2014-01-29
申请人： National Taiwan University of Science and Technology
发明人： Sheng-Yu Peng , Chi-An Lai , Chiang-Hsi Lee , Tzu-Yun Wang
IPC分类号： G06F13/14 , G06F13/28 , G11C16/04 , G11C7/10 , G11C5/06
CPC分类号： G06F13/28 , G06F13/14 , G11C5/066 , G11C7/10 , G11C16/0433 , G11C2207/107 , G11C2216/10
摘要： A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.
摘要翻译：提供一种具有非易失性存储器的串行 - 并行接口电路。控制模块产生多个控制信号，其中控制信号包括读出和写入控制信号和存储器编程控制信号。输入端从外部接收多个数字数据。数字数据被串行传输到输入端。存储器模块耦合到输入端并接收来自控制模块的控制信号。输入端子将数字数据发送到存储器模块。其中一个存储器模块包括存储器单元，并且存储器单元基于高电压控制信号和存储器控制信号存储或发送数字数据的一位。多个输出信号线分别耦合到存储器模块。存储器单元将一位数字数据发送到输出信号线之一。

8. 发明申请

US20160020255A1 MEMORY HOLE BIT LINE STRUCTURES 有权
标题翻译：记忆孔位线结构
公开(公告)号：US20160020255A1
公开(公告)日：2016-01-21
申请号：US14715566
申请日：2015-05-18
申请人： SANDISK 3D LLC
发明人： Perumal Ratnam , Christopher Petti , Tianhong Yan
IPC分类号： H01L27/24 , H01L45/00 , H01L29/786 , G11C13/00
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

9. 发明申请

US20160019961A1 CONTROLLING ADJUSTABLE RESISTANCE BIT LINES CONNECTED TO WORD LINE COMBS 有权
标题翻译：控制连接到字线COMBS的可调节电阻位线
公开(公告)号：US20160019961A1
公开(公告)日：2016-01-21
申请号：US14715583
申请日：2015-05-18
申请人： SANDISK 3D LLC
发明人： Perumal Ratnam , Christopher Petti , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

10. 发明申请

US20150303203A1 NONVOLATILE MEMORY DEVICE HAVING SINGLE-LAYER GATE, METHOD OF OPERATING THE SAME, AND MEMORY CELL ARRAY THEREOF 有权
标题翻译：具有单层门的非易失性存储器件，其操作方法及其存储器单元阵列
公开(公告)号：US20150303203A1
公开(公告)日：2015-10-22
申请号：US14341539
申请日：2014-07-25
申请人： SK hynix Inc.
发明人： Hyun Min SONG
IPC分类号： H01L27/115 , H01L29/78 , G11C16/10 , H01L29/861 , H01L29/423 , G11C16/26 , G11C7/00 , H01L49/02
CPC分类号： G11C16/10 , G11C5/146 , G11C16/0416 , G11C16/14 , G11C16/26 , G11C2216/10 , H01L27/11558 , H01L29/7883
摘要： A nonvolatile memory device includes a single-layer gate, a first area, and a second area. The first area includes a first well region, a first contact region arranged in the first well region, and source and drain regions arranged at both sides of the single-layer gate in the first well region. The second area includes a second well region, a second contact region arranged to overlap a part of the single-layer gate in the second well region, and a third contact region arranged in the second well region.
摘要翻译：非易失性存储器件包括单层栅极，第一区域和第二区域。第一区域包括第一阱区域，布置在第一阱区域中的第一接触区域和布置在第一阱区域中的单层栅极两侧的源极和漏极区域。第二区域包括第二阱区域，布置成与第二阱区域中的单层栅极的一部分重叠的第二接触区域和布置在第二阱区域中的第三接触区域。

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