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41. 发明申请

US20160055110A1 Transaction Filter for On-Chip Communications Network 有权
标题翻译：片上通信网络的事务过滤器
公开(公告)号：US20160055110A1
公开(公告)日：2016-02-25
申请号：US14467164
申请日：2014-08-25
申请人： Apple Inc.
发明人： Gilbert H. Herbeck , Munetoshi Fukami , Manu Gulati
IPC分类号： G06F13/40 , G06F1/32
CPC分类号： G06F13/4022 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172 , Y02D50/20
摘要： A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.
摘要翻译：公开了用于片上通信网络的事务过滤器。在一个实施例中，集成电路（IC）包括多个功能电路块，其中一些可以被置于休眠模式（例如，电源门控）。 IC还包括多个事务过滤器，每个事务过滤器都与唯一的一个功能电路块相关联。响应于其相关联的功能电路块生成事务，给定的事务过滤器可以确定事务处理的功能电路块是否处于睡眠模式。如果确定事务发往当前处于睡眠模式的功能电路块，则事务过滤器可以阻止该事务被传送。

42. 发明申请

US20160049207A1 CONFIGURATION FUSE DATA MANAGEMENT IN A PARTIAL POWER-ON STATE 有权
标题翻译：部分开机状态下的配置保险丝数据管理
公开(公告)号：US20160049207A1
公开(公告)日：2016-02-18
申请号：US14459466
申请日：2014-08-14
申请人： Apple Inc.
发明人： Manu Gulati , Erik P. Machnicki , Gilbert H. Herbeck
IPC分类号： G11C17/18 , G11C7/20 , G11C17/16
CPC分类号： G11C7/20 , G11C17/16 , G11C2029/0407 , G11C2029/4402
摘要： In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.
摘要翻译：在一个实施例中，装置可以包括多个电路块，多个保险丝和电路。电路可以被配置为响应于从关闭模式转换到第一操作模式来确定多个保险丝中的每一个的状态。可以在第一操作模式中启用第一数量的电路块。电路还可以被配置为根据多个保险丝中的一个或多个保险丝的状态并从第一操作模式转换到第二操作模式来初始化第一数量的电路块。可以在第二操作模式中使能小于第一数量的第二数量的电路块。电路还可以被配置为将表示多个保险丝的子集的状态的数据存储到在第二操作模式中启用的第一存储器中。

43. 发明授权

US09201821B2 Interrupt timestamping 有权
标题翻译：中断时间戳
公开(公告)号：US09201821B2
公开(公告)日：2015-12-01
申请号：US13629509
申请日：2012-09-27
申请人： Apple Inc.
发明人： Erik P. Machnicki , Josh P. de Cesare , Manu Gulati
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.
摘要翻译：一种用于保持精确中断时间戳的系统和方法。半导体芯片包括具有多个中断源的接口的中断控制器（IC）。响应于接收到中断，IC复制并记录存储在用于维持全局经过时间的主时基计数器中的值。 IC向对应的处理器发送中断指示。中断服务程序（ISR）或设备驱动程序请求与中断相关联的时间戳。处理器不是向操作系统发送请求以获得存储在主时基计数器中的当前值，而是从IC请求记录的时间戳。 IC识别与中断相关联的存储时间戳，并将其返回给处理器。

44. 发明申请

US20210341317A1 System on a Chip with Always-On Processor 有权
公开(公告)号：US20210341317A1
公开(公告)日：2021-11-04
申请号：US17372764
申请日：2021-07-12
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC分类号： G01D9/00 , G06F13/16 , G06F1/3293 , G06F1/3206 , G06F1/3287
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

45. 发明授权

US10310586B2 Memory power savings in idle display case 有权
公开(公告)号：US10310586B2
公开(公告)日：2019-06-04
申请号：US14980912
申请日：2015-12-28
申请人： Apple Inc.
发明人： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
IPC分类号： G06F1/3218 , G06F1/3234 , G06F3/14 , G09G5/00 , G09G5/393 , G09G5/395 , G06F1/3287 , G06F12/0873
摘要： In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

46. 发明授权

US10261894B2 System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode 有权
公开(公告)号：US10261894B2
公开(公告)日：2019-04-16
申请号：US15447328
申请日：2017-03-02
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC分类号： G06F12/02 , G06F12/06 , G06F1/32 , G06F3/06 , G06F9/44 , G06F13/16 , G06F13/40 , G11C11/406 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F9/4401 , G06F13/42
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

47. 发明申请

US20190012484A1 Unified Addressable Memory 审中-公开
公开(公告)号：US20190012484A1
公开(公告)日：2019-01-10
申请号：US15748893
申请日：2016-08-25
申请人： Apple Inc.
发明人： Manu Gulati , Joseph Sokol, Jr. , Jeffrey R. Wilcox , Bernard J. Semeria , Michael J. Smith
IPC分类号： G06F21/72 , G06F21/78 , G06F12/14 , G06F12/1027 , G06F12/02 , H04L9/08
CPC分类号： G06F21/72 , G06F12/0246 , G06F12/1027 , G06F12/1408 , G06F21/78 , G06F2212/7206 , G06F2212/7208 , G06F2221/2143 , H04L9/0861 , H04L9/0894 , H04L2209/12
摘要： In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

48. 发明授权

US10175905B2 Systems and methods for dynamically switching memory performance states 有权
公开(公告)号：US10175905B2
公开(公告)日：2019-01-08
申请号：US15263833
申请日：2016-09-13
申请人： Apple Inc.
发明人： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
IPC分类号： G06F1/32 , G06F3/06 , G06F1/08 , G06F13/16 , G06F13/42
摘要： Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

49. 发明授权

US10079019B2 Always-on audio control for mobile device 有权
公开(公告)号：US10079019B2
公开(公告)日：2018-09-18
申请号：US14109101
申请日：2013-12-17
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC分类号： G10L15/22 , G10L15/28 , G06F3/16 , G06F1/32 , G10L15/08 , G10L25/48
CPC分类号： G10L15/28 , G06F1/32 , G06F1/3228 , G06F1/3287 , G06F3/165 , G10L15/22 , G10L25/48 , G10L2015/088 , Y02D10/171
摘要： In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

50. 发明授权

US10048720B2 Timebase synchronization 有权
公开(公告)号：US10048720B2
公开(公告)日：2018-08-14
申请号：US15831732
申请日：2017-12-05
申请人： Apple Inc.
发明人： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC分类号： G06F1/12
摘要： In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

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