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41. 发明申请

US20050218041A1 Process and apparatus for separation of hydrocarbons from liquefied natural gas 有权
标题翻译：从液化天然气中分离碳氢化合物的方法和装置
公开(公告)号：US20050218041A1
公开(公告)日：2005-10-06
申请号：US10942842
申请日：2004-09-17
申请人： Nobuhiro Yoshida , Shoichi Yamaguchi , Susumu Ohara , Akhilesh Kumar
发明人： Nobuhiro Yoshida , Shoichi Yamaguchi , Susumu Ohara , Akhilesh Kumar
IPC分类号： B01D3/14 , C07C7/08 , C07C9/06 , C10G5/00 , F25J3/02
CPC分类号： B01D3/14 , C10G5/00 , F25J3/0214 , F25J3/0233 , F25J3/0238 , F25J2200/02 , F25J2205/02 , F25J2230/08 , F25J2230/60 , F25J2235/60
摘要： An apparatus and process for separating a feed liquefied natural gas containing at least methane and a hydrocarbon less volatile the methane, into a product natural gas enriched with methane and lean in hydrocarbon less volatile than methane and a heavier fraction lean in methane and enriched with hydrocarbon less volatile than methane. The process includes heating the feed liquefied natural gas in a heat exchanger, passing the heated fluid into a distillation column, withdrawing the heavier fraction from a bottom of the column, and withdrawing a residue gas from a top of the column. The process also includes liquefying at least part of the residue gas in the heat exchanger, refluxing a part of the liquid portion of the fluid obtained in the liquefying step into the column, and withdrawing, as the product narutal gas, the remainder of the liquid portion.
摘要翻译：一种用于将至少含有甲烷和不易挥发的甲烷的进料液化天然气分离成富含甲烷和贫烃的产物天然气，其比甲烷更不易挥发，而较重馏分贫甲烷和富含烃挥发性低于甲烷。该方法包括在热交换器中加热进料液化天然气，将加热的流体通入蒸馏塔，从塔的底部排出较重的馏分，并从塔的顶部排出残余气体。该方法还包括在热交换器中液化至少一部分残余气体，将在液化步骤中获得的流体的液体部分的一部分回流到塔中，并将作为产物液化气体的剩余液体回收一部分。

42. 发明申请

US20050022100A1 Retraining derived clock receivers 有权
标题翻译：再培训派生的时钟接收器
公开(公告)号：US20050022100A1
公开(公告)日：2005-01-27
申请号：US10623605
申请日：2003-07-22
申请人： Victor Lee , Phanindra Mannava , Akhilesh Kumar , Sanjay Dabral
发明人： Victor Lee , Phanindra Mannava , Akhilesh Kumar , Sanjay Dabral
IPC分类号： H04L1/00 , H04L25/49 , H04Q11/04 , G08C25/00 , G06F11/00 , G06F11/30 , H03M13/00
CPC分类号： H04L1/0061 , H04J2203/0089 , H04L1/0072 , H04L25/4906 , H04L2001/0094
摘要： Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.
摘要翻译：重新接收接收机的系统和方法提供用于确定到接收机的导出时钟数据链路的最小转换密度。基于最小过渡密度产生再培训。在一种方法中，通过为再训练飞行定义控制数据和有效载荷数据来产生再训练飞行。基于控制和有效载荷数据确定重新训练飞行的错误检测数据。控制数据，有效载荷数据和误差检测数据具有足够的过渡以满足最小转换密度。

43. 发明授权

US09674114B2 Modular decoupled crossbar for on-chip router 有权
公开(公告)号：US09674114B2
公开(公告)日：2017-06-06
申请号：US13994801
申请日：2012-02-09
申请人： Dongkook Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
发明人： Dongkook Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
IPC分类号： H04L12/28 , H04W4/00 , H04L12/56 , H04L12/933 , G06F15/173 , G06F15/78
CPC分类号： H04L49/101 , G06F15/17381 , G06F15/7825 , H04L49/109 , H04L49/15 , Y02D10/12 , Y02D10/13
摘要： Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.

44. 发明授权

US08099558B2 Fairness mechanism for starvation prevention in directory-based cache coherence protocols 有权
标题翻译：基于目录的缓存一致性协议中的饥饿预防机制
公开(公告)号：US08099558B2
公开(公告)日：2012-01-17
申请号：US12415929
申请日：2009-03-31
申请人： SeungJoon Park , Ching-Tsun Chou , Akhilesh Kumar
发明人： SeungJoon Park , Ching-Tsun Chou , Akhilesh Kumar
IPC分类号： G06F12/08
CPC分类号： G06F12/0828
摘要： Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e.g., using distributed linked-lists). In turn, the tracked requests may be served in a fair order. Other embodiments are also disclosed.
摘要翻译：描述了与基于目录的高速缓存一致性协议中的挨饿预防公平机制有关的方法和设备。在一个实施例中，可以跟踪来自归属代理的否定确认（nacked）请求（例如，使用分布式链表）。反过来，跟踪的请求可以以公平的顺序提供。还公开了其他实施例。

45. 发明授权

US07996625B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07996625B2
公开(公告)日：2011-08-09
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

46. 发明申请

US20090254712A1 ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS 审中-公开
标题翻译：自适应高速缓存组织用于芯片多重处理器
公开(公告)号：US20090254712A1
公开(公告)日：2009-10-08
申请号：US12061027
申请日：2008-04-02
申请人： Naveen Cherukuri , Ioannis Schoinas , Akhilesh Kumar , Seungjoon Park , Ching-Tsun Chou
发明人： Naveen Cherukuri , Ioannis Schoinas , Akhilesh Kumar , Seungjoon Park , Ching-Tsun Chou
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/084 , G06F2212/271
摘要： A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core 404 may retrieve a data block from a data storage. An initial amorphous cache bank 410 adjacent to the initial processing core 404 may store an initial data block copy 422. A home bank directory 424 may register the initial data block copy 422.
摘要翻译：公开了一种方法，芯片多处理器瓦片和具有非晶缓存的芯片多处理器。初始处理核心404可以从数据存储器检索数据块。与初始处理核心404相邻的初始非晶缓存组410可以存储初始数据块副本422.归属库目录424可以注册初始数据块拷贝422。

47. 发明申请

US20070130353A1 Link level retry scheme 有权
标题翻译：链路级重试方案
公开(公告)号：US20070130353A1
公开(公告)日：2007-06-07
申请号：US11326982
申请日：2006-01-06
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra Mannava , Rajee Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra Mannava , Rajee Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G06F15/16
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
摘要翻译：提供了一个链路层系统。链路层系统是第一链路层控制模块和用于存储传输的数据分组的重试队列。重试控制模块耦合到第一链路层控制模块，当第一链路层控制模块接收到确认位时，引导重试队列丢弃所发送的数据分组。

48. 发明授权

US07167957B2 Mechanism for handling explicit writeback in a cache coherent multi-node architecture 有权
标题翻译：在缓存一致多节点架构中处理显式回写的机制
公开(公告)号：US07167957B2
公开(公告)日：2007-01-23
申请号：US10896151
申请日：2004-07-20
申请人： Manoj Khare , Lily P. Looi , Akhilesh Kumar
发明人： Manoj Khare , Lily P. Looi , Akhilesh Kumar
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0828
摘要： A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
摘要翻译：描述了一种用于在高速缓存相关多节点架构中处理显式回写的机制的方法和装置。在一个实施例中，本发明是一种方法。该方法包括在相干存储器系统中接收与第一行数据有关的读取请求。该方法还包括在接收到读取请求的同时接收与第一行数据相关的写入请求。该方法还包括检测读请求和写请求都与第一行相关。该方法还包括确定读和写请求的哪个请求应首先进行。此外，该方法包括完成应该首先进行的读取和写入请求的请求。

49. 发明授权

US07124252B1 Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system 有权
标题翻译：用于将有序输入/输出事务流水线分配存储器，高速缓存一致的多处理器系统中的相干存储器的方法和装置
公开(公告)号：US07124252B1
公开(公告)日：2006-10-17
申请号：US09643380
申请日：2000-08-21
申请人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Kenneth C. Creta
发明人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Kenneth C. Creta
IPC分类号： G06F13/14
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0835
摘要： An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.
摘要翻译：用于将有序输入/输出事务流水线分配到分布式存储器，高速缓存一致的多处理器系统中的相干存储器的方法。响应于来自指向分布式相干存储器的输入/输出总线的事务，预取引擎从分布式相干存储器预取数据。输入/输出相干缓存缓冲器接收预取数据，并与分布式，相干存储器和系统中的其他高速缓存代理保持一致。

50. 发明授权

US06976129B2 Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture 有权
标题翻译：用于将已知事务长度的I / O事务处理到缓存一致多节点体系结构中的相干内存的机制
公开(公告)号：US06976129B2
公开(公告)日：2005-12-13
申请号：US10261944
申请日：2002-09-30
申请人： Kenneth C. Creta , Manoj Khare , Lily P. Looi , Akhilesh Kumar
发明人： Kenneth C. Creta , Manoj Khare , Lily P. Looi , Akhilesh Kumar
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0813 , Y10S707/99952
摘要： A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.
摘要翻译：描述了一种用于处理具有已知事务长度的I / O事务的机制的方法和装置，用于缓存相关多节点架构中的相干存储器。在一个实施例中，本发明是一种方法。该方法包括接收对数据线的当前副本的请求。该方法还包括在高速缓存相干多节点系统内找到数据线。该方法还包括复制数据线而不干扰与数据线相关联的状态。该方法还包括响应于该请求提供数据线的副本。该方法还包括基于事务的已知事务长度来确定数据行是否是事务的最后数据行。

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