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1. 发明授权

US09418011B2 Region based technique for accurately predicting memory accesses 有权
标题翻译：用于准确预测存储器访问的基于区域的技术
公开(公告)号：US09418011B2
公开(公告)日：2016-08-16
申请号：US12821935
申请日：2010-06-23
申请人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
发明人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024
摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。还描述和要求保护其他实施例。

2. 发明授权

US08990506B2 Replacing cache lines in a cache memory based at least in part on cache coherency state information 有权
标题翻译：至少部分地基于高速缓存一致性状态信息来替换缓存存储器中的高速缓存行
公开(公告)号：US08990506B2
公开(公告)日：2015-03-24
申请号：US12639191
申请日：2009-12-16
申请人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
发明人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/084 , G06F12/126
摘要： In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括高速缓存存储器，其包括高速缓存行，每个高速缓存行具有包括状态部分的标签字段，该状态部分存储存储在该行中的数据的高速缓存一致性状态，以及权重部分，用于存储对应于数据。在各种实现中，权重可以基于高速缓存一致性状态和数据的使用的新近。描述和要求保护其他实施例。

3. 发明申请

US20140376557A1 MODULAR DECOUPLED CROSSBAR FOR ON-CHIP ROUTER 有权
标题翻译：用于片上路由器的模块化解交叉
公开(公告)号：US20140376557A1
公开(公告)日：2014-12-25
申请号：US13994801
申请日：2012-02-09
申请人： Dongkonk Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
发明人： Dongkonk Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
IPC分类号： H04L12/933
CPC分类号： H04L49/101 , G06F15/17381 , G06F15/7825 , H04L49/109 , H04L49/15 , Y02D10/12 , Y02D10/13
摘要： Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.
摘要翻译：布局感知的模块化去耦交叉开关和路由器，用于片上互连和相关的微架构和操作方法。公开了一种称为MoDe-X（模块化解耦交叉开关）的交叉开关和路由器架构，其支持用于2D网状互连的5端口路由，并且通过使用去耦的行和列子交叉模块与馈线布线和控制逻辑这可以在行和列子交叉杆模块上的端口之间进行路由。相应的MoDe-X路由器支持各种路由器输入和输出端口组合之间的5端口路由，与传统的5×5交叉开关设计和实现相比，可以减少路由器面积和功耗。 MoDe-X微架构可以配置为支持单端口和双端口注入配置。

4. 发明申请

US20140181477A1 Compressing Execution Cycles For Divergent Execution In A Single Instruction Multiple Data (SIMD) Processor 有权
标题翻译：在单指令多数据（SIMD）处理器中压缩执行循环
公开(公告)号：US20140181477A1
公开(公告)日：2014-06-26
申请号：US13724633
申请日：2012-12-21
申请人： Aniruddha S. Vaidya , Anahita Shayesteh , Dong Hyuk Woo , Saikat Saharoy , Mani Azimi
发明人： Aniruddha S. Vaidya , Anahita Shayesteh , Dong Hyuk Woo , Saikat Saharoy , Mani Azimi
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30058 , G06F9/30072 , G06F9/30181 , G06F9/3887
摘要： In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有向量执行单元的处理器，用于对具有多个单独数据元素的向量执行向量指令，其中向量指令具有第一宽度，并且向量执行单元具有较小宽度。所述处理器还包括耦合到所述向量执行单元的控制逻辑，以便当所述各个数据元素中的至少一些不被所述向量指令操作时，压缩执行所述向量指令时所消耗的执行周期数。描述和要求保护其他实施例。

5. 发明申请

US20110320762A1 REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES 有权
标题翻译：准确预测存储器访问的基于区域的技术
公开(公告)号：US20110320762A1
公开(公告)日：2011-12-29
申请号：US12821935
申请日：2010-06-23
申请人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
发明人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/10
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024
摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。还描述和要求保护其他实施例。

6. 发明授权

US08683136B2 Apparatus and method for improving data prefetching efficiency using history based prefetching 有权
标题翻译：用于使用基于历史的预取来提高数据预取效率的装置和方法
公开(公告)号：US08683136B2
公开(公告)日：2014-03-25
申请号：US12976775
申请日：2010-12-22
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

7. 发明申请

US20120166733A1 APPARATUS AND METHOD FOR IMPROVING DATA PREFETCHING EFFICIENCY USING HISTORY BASED PREFETCHING 有权
标题翻译：使用基于历史的预编译改进数据预取效率的装置和方法
公开(公告)号：US20120166733A1
公开(公告)日：2012-06-28
申请号：US12976775
申请日：2010-12-22
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

8. 发明授权

US06263397B1 Mechanism for delivering interrupt messages 有权
标题翻译：传递中断消息的机制
公开(公告)号：US06263397B1
公开(公告)日：2001-07-17
申请号：US09206995
申请日：1998-12-07
申请人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , M. Jayakumar
发明人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , M. Jayakumar
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.
摘要翻译： I / O代理通过芯片组将中断消息传递到连接到多个处理器的系统总线。中断消息包括事务类型和目标标识。系统总线上的服务处理器将目的地标识与其自己的标识相匹配，以确定它是否是中断消息的预期接收者。 I / O代理将与中断相关的数据写入芯片组内的缓冲队列。在发送中断消息之前，芯片组会自动将缓冲队列的内容刷新到主存储器。中断传送机制避免了芯片组和I / O代理之间的握手操作的复杂性和延迟。

9. 发明授权

US5848279A Mechanism for delivering interrupt messages 失效
标题翻译：传递中断消息的机制
公开(公告)号：US5848279A
公开(公告)日：1998-12-08
申请号：US777308
申请日：1996-12-27
申请人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , Muthurajan Jayakumar
发明人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , Muthurajan Jayakumar
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.
摘要翻译： I / O代理通过芯片组将中断消息传递到连接到多个处理器的系统总线。中断消息包括事务类型和目标标识。系统总线上的服务处理器将目的地标识与其自己的标识相匹配，以确定它是否是中断消息的预期接收者。 I / O代理将与中断相关的数据写入芯片组内的缓冲队列。在发送中断消息之前，芯片组会自动将缓冲队列的内容刷新到主存储器。中断传送机制避免了芯片组和I / O代理之间的握手操作的复杂性和延迟。

10. 发明授权

US09674114B2 Modular decoupled crossbar for on-chip router 有权
公开(公告)号：US09674114B2
公开(公告)日：2017-06-06
申请号：US13994801
申请日：2012-02-09
申请人： Dongkook Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
发明人： Dongkook Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
IPC分类号： H04L12/28 , H04W4/00 , H04L12/56 , H04L12/933 , G06F15/173 , G06F15/78
CPC分类号： H04L49/101 , G06F15/17381 , G06F15/7825 , H04L49/109 , H04L49/15 , Y02D10/12 , Y02D10/13
摘要： Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.

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