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41. 发明授权

US07613199B1 Systems and methods for permitting queues to oversubscribe 有权
标题翻译：允许队列超额认购的系统和方法
公开(公告)号：US07613199B1
公开(公告)日：2009-11-03
申请号：US11756443
申请日：2007-05-31
申请人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
发明人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
IPC分类号： H04L12/28
CPC分类号： H04L47/525 , H04L47/50 , H04L47/522
摘要： A system permits queues to use more than an allocated amount of bandwidth. The system allocates an amount of bandwidth to each of the queues and determines whether any of the queues is using less than the allocated amount of bandwidth. If so, the system reallocates the allocated bandwidth from one of the queues to at least one other one of the queues based on the amount of bandwidth used by each of the queues.
摘要翻译：系统允许队列使用多于分配的带宽量。系统为每个队列分配一定量的带宽，并确定任何一个队列是否使用小于分配的带宽量。如果是这样，则系统根据每个队列使用的带宽量，将所分配的带宽从一个队列重新分配到至少一个其他队列。

42. 发明授权

US07512080B1 Forwarding tree having multiple bit and intermediate bit pattern comparisons 有权
标题翻译：具有多位和中间位模式比较的转发树
公开(公告)号：US07512080B1
公开(公告)日：2009-03-31
申请号：US11305847
申请日：2005-12-16
申请人： Kireeti Kompella , Jean Marc Frailong , Pradeep Sindhu
发明人： Kireeti Kompella , Jean Marc Frailong , Pradeep Sindhu
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L45/7457
摘要： Principles of the invention are directed to techniques for allowing a router forwarding packets within a computer network to perform two or more forwarding tree decisions per memory access. The router may implement forwarding information in the form of a radix tree having a number of nodes, and received packets may contain keys identifying a packet destination. The router may traverse the tree by testing two or more path control bits within the key per each of the traversed nodes. The values of the path control bits in the key determine the path traversed along the tree. The router also stores intermediate bit patterns at each node and tests intermediate bits in the key to determine whether a particular node is the best match to the routing prefix contained in the key, thereby eliminating a need to backtrack up the tree.
摘要翻译：本发明的原理涉及允许路由器在计算机网络内转发分组以对每个存储器访问执行两个或多个转发树决策的技术。路由器可以以具有多个节点的小树形式实现转发信息，并且接收的分组可以包含标识分组目的地的密钥。路由器可以通过测试每个遍历节点内的密钥内的两个或多个路径控制位来遍历树。密钥中的路径控制位的值确定沿着树路径。路由器还在每个节点处存储中间位模式，并测试密钥中的中间位，以确定特定节点是否与密钥中包含的路由前缀最匹配，从而无需追溯树。

43. 发明授权

US07283470B1 Systems and methods for dropping data using a drop profile 有权
标题翻译：使用放置配置文件删除数据的系统和方法
公开(公告)号：US07283470B1
公开(公告)日：2007-10-16
申请号：US10207002
申请日：2002-07-30
申请人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
发明人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
IPC分类号： G01R31/08
CPC分类号： H04L47/32 , H04L47/10 , H04L47/23 , H04L47/30 , H04L47/326 , H04L49/90 , H04L49/9078
摘要： A system selectively drops data from queues. The system includes a drop table that stores drop probabilities. The system selects one of the queues to examine and generates an index into the drop table to identify one of the drop probabilities for the examined queue. The system then determines whether to drop data from the examined queue based on the identified drop probability.
摘要翻译：系统有选择地从队列中删除数据。该系统包括存储丢弃概率的丢弃表。系统选择一个队列来检查并生成一个索引到丢包表中，以识别已检查队列的一个丢弃概率。系统然后基于所识别的丢弃概率来确定是否从检查的队列中丢弃数据。

44. 发明授权

US07215637B1 Systems and methods for processing packets 有权
标题翻译：用于处理数据包的系统和方法
公开(公告)号：US07215637B1
公开(公告)日：2007-05-08
申请号：US10017719
申请日：2001-12-14
申请人： Dennis C. Ferguson , Rajiv Patel , Gerald Cheung , Pradeep Sindhu
发明人： Dennis C. Ferguson , Rajiv Patel , Gerald Cheung , Pradeep Sindhu
IPC分类号： H04L12/26
CPC分类号： H04L45/745 , H04L45/00 , H04L45/60 , H04L45/7457 , H04L47/10 , H04L47/11 , H04L47/125 , H04L47/20 , H04L49/205 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L63/0227 , H04L63/1458 , H04L69/22
摘要： Methods and devices for processing packets are provided. The processing device may include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data units.
摘要翻译：提供了处理数据包的方法和设备。处理装置可以包括用于接收包含各个分组的报头信息的数据单元的输入接口; 第一模块，可配置为基于所接收的数据单元执行分组过滤; 第二模块，其可配置为基于所接收的数据单元执行流量分析; 第三模块，可配置为基于所接收的数据单元执行负载平衡; 以及第四模块，其可配置为基于所接收的数据单元执行路线查找。

45. 发明授权

US07032082B1 Centralized memory allocation with write pointer drift correction 有权
标题翻译：集中存储器分配与写指针漂移校正
公开(公告)号：US07032082B1
公开(公告)日：2006-04-18
申请号：US09942623
申请日：2001-08-31
申请人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
发明人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：用于写入数据的系统包括存储器，至少一个存储器控制器和控制逻辑。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复并确定答复中的地址是否与包含在与其他存储器控制器相关联的应答中的地址相差阈值。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

46. 发明授权

US5497480A Broadcast demap for deallocating memory pages in a multiprocessor system 失效
标题翻译：在多处理器系统中解除分配内存页的广播解映射
公开(公告)号：US5497480A
公开(公告)日：1996-03-05
申请号：US282170
申请日：1994-07-29
申请人： Norman M. Hayes , Pradeep Sindhu , Jean-Marc Frailong , Sunil Nanda
发明人： Norman M. Hayes , Pradeep Sindhu , Jean-Marc Frailong , Sunil Nanda
IPC分类号： G06F12/08 , G06F12/10 , G06F13/364 , G06F12/12 , H04J3/24
CPC分类号： G06F12/1027 , G06F12/0831 , G06F13/364 , G06F2212/682
摘要： A method and apparatus for removing a page table entry from a plurality of translation lookaside buffers ("TLBs") in a multiprocessor computer system. The multiprocessor computer system includes at least two processors coupled to a packet-switched bus. Page table entries are removed from a plurality of TLBs in the multiprocessor computer system by first broadcasting a demap request packet on the packet-switched bus in response to one of the processors requesting that a page table entry be removed from its associated TLB. The demap request packet includes a virtual address and context information specifying this page table entry. Controllers reply to the demap request packet by sending a first reply packet to the controller that sent the original demap request packet to indicate receipt of the demap request packet. If a controller removes the page table entry from its associated TLB, that controller sends a second demap reply packet to indicate that the page table entry has been removed from its associated TLB.
摘要翻译：一种用于从多处理器计算机系统中的多个翻译后备缓冲器（“TLB”）中移除页表条目的方法和装置。多处理器计算机系统包括耦合到分组交换总线的至少两个处理器。通过首先在分组交换总线上广播解映射请求分组来响应于处理器中的一个请求从其相关联的TLB中移除页表项，从多个处理器计算机系统中的多个TLB中移除页表项。解映射请求分组包括指定该页表项的虚拟地址和上下文信息。控制器通过向发送原始解映射请求分组的控制器发送第一应答分组来响应解映射请求分组，以指示解映射请求分组的接收。如果控制器从相关联的TLB中删除页表项，则该控制器发送第二解映射应答分组以指示该页表项已经从其关联的TLB中移除。

47. 发明授权

US5265233A Method and apparatus for providing total and partial store ordering for a memory in multi-processor system 失效
标题翻译：用于在多处理器系统中为存储器提供全部和部分存储顺序的方法和装置
公开(公告)号：US5265233A
公开(公告)日：1993-11-23
申请号：US702781
申请日：1991-05-17
申请人： Jean-Marc Frailong , Pradeep Sindhu , Michel Cekleov , Michael Powell , Eric Jensen
发明人： Jean-Marc Frailong , Pradeep Sindhu , Michel Cekleov , Michael Powell , Eric Jensen
IPC分类号： G06F12/00 , G06F9/30 , G06F9/312 , G06F9/38 , G06F12/08 , G06F15/177 , G06F13/14
CPC分类号： G06F9/3004 , G06F12/0833 , G06F9/30054 , G06F9/30079 , G06F9/30087 , G06F9/3834
摘要： An improved memory model and implementation is disclosed. The memory model includes a Total Store Ordering (TSO) and Partial Store Ordering (PSO) memory model to provide a partial order for the memory operations which are issued by multiple processors. The TSO memory model includes a FIFO Store Buffer for Store, and Atomic Load-Store operations. The Load operations are not placed in the FIFO Store Buffer. The Load operation checks for a value stored in the same location in the FIFO Store Buffer; if no such value is found, then requested value is returned from memory. The PSO model also includes a Store Buffer for Store, and Atomic Load-Store operations. However, unlike the TSO model, the Store Buffer in the PSO model is not FIFO. The processors in the PSO model may issue the Store and Atomic Load-Store in a certain order; however, such operations may be executed by memory out of the order issued by the processors. The execution order is assured only by address matching and the STBAR operation. Two Store operations separated by a STBAR operations guarantees memory will execute the operations in an order issued by the processors. Load operations in the PSO model are not placed in the Store Buffer. The Load operation first checks for a value stored in the same location in the Store Buffer; if no such value is found, then the requested value is returned from memory.

48. 发明授权

US09407457B2 Apparatuses for a wired/wireless network architecture 有权
标题翻译：有线/无线网络架构的设备
公开(公告)号：US09407457B2
公开(公告)日：2016-08-02
申请号：US13252852
申请日：2011-10-04
申请人： Pradeep Sindhu , Abhijit Choudhury , James Murphy , Raghavendra Mallya , Pranay Pogde , Phalguni Nanda , Jayabharat Boddu , Gunes Aybay , Anjan Venkatramani
发明人： Pradeep Sindhu , Abhijit Choudhury , James Murphy , Raghavendra Mallya , Pranay Pogde , Phalguni Nanda , Jayabharat Boddu , Gunes Aybay , Anjan Venkatramani
IPC分类号： H04L12/46 , H04L12/723
CPC分类号： H04L45/50 , H04L12/4633 , H04W84/12 , H04W88/08
摘要： In some embodiments, an apparatus comprises a core network node and a control module within an enterprise network architecture. The core network node is configured to be operatively coupled to a set of wired network nodes and a set of wireless network nodes. The core network node is configured to receive a first tunneled packet associated with a first session from a wired network node from the set of wired network nodes. The core network node is configured to also receive a second tunneled packet associated with a second session from a wireless network node from the set of wireless network nodes through intervening wired network nodes from the set of wired network nodes. The control module is operatively coupled to the core network node. The control module is configured to manage the first session and the second session.
摘要翻译：在一些实施例中，装置包括企业网络架构内的核心网络节点和控制模块。核心网络节点被配置为可操作地耦合到一组有线网络节点和一组无线网络节点。核心网络节点被配置为从有线网络节点组从有线网络节点接收与第一会话关联的第一隧道化分组。核心网络节点被配置为通过来自有线网络节点组的中间有线网络节点，还从无线网络节点组从无线网络节点接收与第二会话关联的第二隧道化分组。控制模块可操作地耦合到核心网络节点。控制模块被配置为管理第一会话和第二会话。

49. 发明授权

US08958432B2 Methods and apparatus related to a flexible data center security architecture 有权
标题翻译：与灵活的数据中心安全架构相关的方法和设备
公开(公告)号：US08958432B2
公开(公告)日：2015-02-17
申请号：US13608799
申请日：2012-09-10
申请人： Pradeep Sindhu , Gunes Aybay , Jean-Marc Frailong , Anjan Venkatramani , Quaizar Vohra
发明人： Pradeep Sindhu , Gunes Aybay , Jean-Marc Frailong , Anjan Venkatramani , Quaizar Vohra
IPC分类号： H04L12/70 , H04L12/24 , H04L12/947 , H04L12/931
CPC分类号： H04L49/30 , H04L41/0806 , H04L41/0846 , H04L49/257 , H04L49/35 , H04L49/356 , H04L63/101
摘要： In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.
摘要翻译：在一个实施例中，边缘设备可被配置为耦合到多级交换结构和外围处理设备。边缘设备和多级交换结构可以共同定义单个逻辑实体。来自边缘设备的第一边缘设备可以被配置为从外围处理设备耦合到第一外围处理设备。来自边缘设备的第二边缘设备可以被配置为从外围处理设备耦合到第二外围处理设备。第一边缘设备可以被配置为使得可以在第一外围处理设备处定义包括第一虚拟资源的虚拟资源。网络管理模块，其耦合到所述边缘设备并且被配置为提供所述虚拟资源，使得所述第一虚拟资源可以从所述第一外围处理设备迁移到所述第二外围处理设备。

50. 发明授权

US08804711B2 Methods and apparatus related to a modular switch architecture 有权
标题翻译：与模块化交换架构相关的方法和设备
公开(公告)号：US08804711B2
公开(公告)日：2014-08-12
申请号：US12345502
申请日：2008-12-29
申请人： Gunes Aybay , Jaya Bandyopadhyay , Jean-Marc Frailong , Pradeep Sindhu , Philip A. Thomas , Anjan Venkatramani
发明人： Gunes Aybay , Jaya Bandyopadhyay , Jean-Marc Frailong , Pradeep Sindhu , Philip A. Thomas , Anjan Venkatramani
IPC分类号： H04L12/58 , H04L12/56
CPC分类号： H04L49/15 , H04L49/10 , H04L49/45
摘要： In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.
摘要翻译：在一些实施例中，装置包括第一壳体，第二壳体和至少一个电缆。第一壳体包括交换结构的第一接口卡。第二壳体包括交换结构的第二接口卡和交换结构的第三接口卡。交换结构的第二接口卡经由中间平面操作和物理地耦合到交换结构的第三接口卡。第二接口卡限定了与第三接口卡所定义的平面不平行的平面和由中平面限定的平面。由第三接口卡定义的平面与由第二接口卡定义的平面和由中平面限定的平面不平行。电缆被配置为将第一接口卡可操作地耦合到第二接口卡。

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