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41. 发明授权

US07944235B1 High-speed serial interface circuitry for programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路的高速串行接口电路
公开(公告)号：US07944235B1
公开(公告)日：2011-05-17
申请号：US12709360
申请日：2010-02-19
申请人： Sergey Shumarayev , Thungoc M. Tran , Simardeep Maangat , Wilson Wong
发明人： Sergey Shumarayev , Thungoc M. Tran , Simardeep Maangat , Wilson Wong
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.
摘要翻译：高速串行接口（“HSSI”）收发器电路（例如，在可编程逻辑器件（“PLD”）集成电路上）包括具有自适应均衡能力的输入缓冲器电路。收发器电路还包括输出驱动器，其可以包括预加重功能（优选可控地设置）。提供了可选择的环回电路，用于使输入缓冲器的输出信号基本上直接施加到输出驱动器。环回电路可以包括环回驱动器，其可以基本上仅在环回操作需要时被导通。

42. 发明申请

US20090302888A1 INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER 有权
标题翻译：在高数据速率HSSI接收器中提高灵敏度和降低偏移
公开(公告)号：US20090302888A1
公开(公告)日：2009-12-10
申请号：US12134777
申请日：2008-06-06
申请人： Sergey Shumarayev , Thungoc M. Tran , Wilson Wong , Simardeep Maangat
发明人： Sergey Shumarayev , Thungoc M. Tran , Wilson Wong , Simardeep Maangat
IPC分类号： H03K19/0175
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuits elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译：集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。在一个实施例中，缓冲电路具有可变值电路元件。进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。在另一个实施例中，多级缓冲器的每个放大级提供可变增益。级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。在级联开始时也可以提供一个额外的前级放大器级。

43. 发明授权

US07639993B1 Power supply circuitry for data signal transceivers on integrated circuits 有权
标题翻译：集成电路上数据信号收发器的电源电路
公开(公告)号：US07639993B1
公开(公告)日：2009-12-29
申请号：US11295391
申请日：2005-12-05
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
IPC分类号： H04B1/04
CPC分类号： H04L7/033
摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.
摘要翻译：集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

44. 发明授权

US09246715B1 Pre-emphasis circuitry including a pre-emphasis voltage variation compensation engine 有权
标题翻译：预加重电路，包括预加重电压变化补偿引擎
公开(公告)号：US09246715B1
公开(公告)日：2016-01-26
申请号：US12432136
申请日：2009-04-29
申请人： Allen Chan , Wilson Wong , Tim Tri Hoang
发明人： Allen Chan , Wilson Wong , Tim Tri Hoang
IPC分类号： H03K19/094 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0272 , H03K19/00315 , H03K19/00361
摘要： A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.
摘要翻译：一种预加重电路，其包括（1）具有转移检测电路的预加重电压变化补偿（PVVC）引擎和（2）耦合到PVVC引擎的补偿驱动器。在一个实施例中，补偿驱动器减少由预加重电路提供的预加重中的数据相关电压变化。在一个实施例中，响应于由PVVC引擎检测到的预定数据模式，补偿驱动器为预加重电路的性能关键电容性节点提供额外的提升。额外的升压会导致性能关键的电容性节点更快地充电或放电。在一个实施例中，PVVC引擎还包括耦合到转换检测电路的数字有限脉冲响应（FIR）滤波器。此外，在一个实施例中，PVVC引擎还包括耦合到数字FIR滤波器的FIR延迟电路和耦合到数字FIR滤波器和FIR延迟电路的同步器电路，其中FIR延迟电路将等待时间延迟到由转换检测电路和同步器电路将要发送到主驱动器，预加重驱动器和补偿驱动器的数据同步。

45. 发明授权

US08189729B2 Wide range and dynamically reconfigurable clock data recovery architecture 有权
标题翻译：宽范围和动态可重构的时钟数据恢复架构
公开(公告)号：US08189729B2
公开(公告)日：2012-05-29
申请号：US11329197
申请日：2006-01-09
申请人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
发明人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H03K19/17732 , H03K19/17744 , H03L7/10 , H04L7/0004 , H04L7/033
摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.
摘要翻译：宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。为了支持广泛的数据速率，CDR架构包括多个操作参数。这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。可以在不关闭电路或PLD的情况下动态重新编程参数。这允许CDR电路在各种标准和协议之间进行即时切换。

46. 发明授权

US07590207B1 Modular serial interface in programmable logic device 有权
标题翻译：可编程逻辑器件中的模块化串行接口
公开(公告)号：US07590207B1
公开(公告)日：2009-09-15
申请号：US11256346
申请日：2005-10-20
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.
摘要翻译：用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环）。这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

47. 发明授权

US08416845B1 Decision feedback equalization for variable input amplitude 有权
标题翻译：用于可变输入幅度的判决反馈均衡
公开(公告)号：US08416845B1
公开(公告)日：2013-04-09
申请号：US11484285
申请日：2006-07-11
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03K5/1532
摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.
摘要翻译：提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。抽头系数可以由均衡电路自动调整。

48. 发明授权

US07557615B1 High-speed serial data transmitter architecture 有权
标题翻译：高速串行数据发射机架构
公开(公告)号：US07557615B1
公开(公告)日：2009-07-07
申请号：US12069353
申请日：2008-02-08
申请人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
发明人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压，和（6）电气空闲模式。

49. 发明授权

US08836443B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08836443B2
公开(公告)日：2014-09-16
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L23/66 , H03B5/08 , H03C3/22 , H01F27/29 , H03B5/12 , H01F27/28 , H01F21/12
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

50. 发明授权

US08299802B2 Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics 有权
标题翻译：使用动态模拟测试多路复用器对系统中的模拟信号进行数字化的方法进行诊断
公开(公告)号：US08299802B2
公开(公告)日：2012-10-30
申请号：US12263290
申请日：2008-10-31
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev
IPC分类号： G01R31/02
CPC分类号： G01R31/3167
摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.
摘要翻译：提出了一种能够监视模拟模块内的模拟电压的集成电路。集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

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