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1. 发明授权

US11315208B2 Conceptual representation of business processes for cross-domain mapping 有权
公开(公告)号：US11315208B2
公开(公告)日：2022-04-26
申请号：US12842350
申请日：2010-07-23
申请人： Gregory Adams , Vadim Berestetsky , Dorian Birsan , Allen Chan , John Steinbacher
发明人： Gregory Adams , Vadim Berestetsky , Dorian Birsan , Allen Chan , John Steinbacher
IPC分类号： G06Q99/00 , G06Q10/06
摘要： A computer-implemented method, system, and computer program product for cross-domain mapping between a business process modeler domain and an implementation domain are provided. The method includes accessing a business concept registry on a data storage device including business concepts with mapping for the business process modeler domain and the implementation domain. The method also includes creating a model with one or more of the business concepts interconnected to represent a business process in the business process modeler domain, and exporting the model from the business process modeler domain to the implementation domain according to the business concept mapping of the business concept registry.

2. 发明申请

US20120280724A1 APPARATUS AND METHODS OF REDUCING PRE-EMPHASIS VOLTAGE JITTER 有权
标题翻译：降低前置电压抖动器的装置和方法
公开(公告)号：US20120280724A1
公开(公告)日：2012-11-08
申请号：US13102918
申请日：2011-05-06
申请人： Allen CHAN , Wilson WONG
发明人： Allen CHAN , Wilson WONG
IPC分类号： H03K3/00
CPC分类号： H04B3/06 , H04L25/0272 , H04L25/03343
摘要： One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及一种驱动具有最小电压抖动的预加重的传输信号的方法。接收数字数据信号，产生预加重信号。预加重信号可以是数字数据信号的相移和缩放版本。通过在驱动器开关电路内的数字数据信号中加上预加重信号，同时对驱动器开关电路的电流源施加低通滤波来产生输出信号。还公开了其它实施例，方面和特征。

3. 发明授权

US08290750B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US08290750B1
公开(公告)日：2012-10-16
申请号：US13036437
申请日：2011-02-28
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： H03F1/26
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

4. 发明授权

US08073040B1 Serial communications control plane with optional features 有权
标题翻译：具有可选功能的串行通信控制平面
公开(公告)号：US08073040B1
公开(公告)日：2011-12-06
申请号：US10923540
申请日：2004-08-20
申请人： Allen Chan , Faisal Dada , Karl Lu , Bryon Moyer , Venkat Yadavalli , Arye Ziklik
发明人： Allen Chan , Faisal Dada , Karl Lu , Bryon Moyer , Venkat Yadavalli , Arye Ziklik
IPC分类号： H04B1/38
CPC分类号： G06F13/4295 , G06F13/4072
摘要： A serial communications protocol is provided that has mandatory features such as an idle code feature and optional features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature, an optional clock tolerance compensation feature, an optional flow control feature, and an optional retry-on-error feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional features are implemented are able to perform the associated functions. Integrated circuits in which the optional features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.
摘要翻译：提供串行通信协议，其具有诸如空闲代码特征和可选特征的强制特征，例如可选的自动车道极性反转特征和可选的自动车道顺序反转特征，可选的时钟容限补偿特征，可选的流量控制特征，和可选的重试错误功能。希望创建符合协议的集成电路设计的用户可以选择包括或不包括可选功能。实现可选功能的集成电路能够执行相关功能。其中可选功能尚未实现的集成电路不能执行这些功能，但可以使用更少的电路资源来制造。

5. 发明申请

US20110066566A1 CONCEPTUAL REPRESENTATION OF BUSINESS PROCESSES FOR CROSS-DOMAIN MAPPING 审中-公开
标题翻译：概念表示跨域映射的业务流程
公开(公告)号：US20110066566A1
公开(公告)日：2011-03-17
申请号：US12842350
申请日：2010-07-23
申请人： Gregory Adams , Vadim Berestetsky , Dorian Birsan , Allen Chan , John Steinbacher
发明人： Gregory Adams , Vadim Berestetsky , Dorian Birsan , Allen Chan , John Steinbacher
IPC分类号： G06Q10/00
CPC分类号： G06Q99/00 , G06Q10/067
摘要： A computer-implemented method, system, and computer program product for cross-domain mapping between a business process modeler domain and an implementation domain are provided. The method includes accessing a business concept registry on a data storage device including business concepts with mapping for the business process modeler domain and the implementation domain. The method also includes creating a model with one or more of the business concepts interconnected to represent a business process in the business process modeler domain, and exporting the model from the business process modeler domain to the implementation domain according to the business concept mapping of the business concept registry.
摘要翻译：提供了一种计算机实现的方法，系统和计算机程序产品，用于业务流程建模器域和实现域之间的跨域映射。该方法包括访问数据存储设备上的业务概念注册表，其中包括业务概念与业务流程建模器域和实现域的映射。该方法还包括创建具有互连的一个或多个业务概念的模型以表示业务流程建模器域中的业务流程，以及根据业务流程建模器域的业务概念映射将模型从业务流程建模器域导出到实现域业务概念注册。

6. 发明授权

US07602212B1 Flexible high-speed serial interface architectures for programmable integrated circuit devices 有权
标题翻译：用于可编程集成电路器件的灵活的高速串行接口架构
公开(公告)号：US07602212B1
公开(公告)日：2009-10-13
申请号：US11904003
申请日：2007-09-24
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17744
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.
摘要翻译：集成电路（例如，可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括高速串行数据信号接口通道，其中一些包括更多专用于执行各种高速串行数据接口功能比其他那些通道有。为了增加可以使用更多功能丰富的信道中的这种电路的灵活性，提供路由选择性地允许较不富有特征的信道使用更多功能丰富的信道的某些专用电路，其不是本身使用全部其专用电路。

7. 发明申请

US20090154591A1 High-speed serial data signal transmitter driver circuitry 审中-公开
标题翻译：高速串行数据信号发射器驱动电路
公开(公告)号：US20090154591A1
公开(公告)日：2009-06-18
申请号：US12002540
申请日：2007-12-17
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Weiqi Ding
IPC分类号： H04L27/00
CPC分类号： H04L25/028
摘要： Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.
摘要翻译：用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

8. 发明授权

US07356756B1 Serial communications data path with optional features 有权
标题翻译：具有可选功能的串行通信数据路径
公开(公告)号：US07356756B1
公开(公告)日：2008-04-08
申请号：US10923376
申请日：2004-08-20
申请人： Allen Chan , Faisal Dada , Karl Lu , Bryon Moyer , Venkat Yadavalli , Arye Ziklik
发明人： Allen Chan , Faisal Dada , Karl Lu , Bryon Moyer , Venkat Yadavalli , Arye Ziklik
IPC分类号： H03M13/00
CPC分类号： H04L1/0083 , H03M13/356 , H04L2001/0098
摘要： Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.
摘要翻译：提供符合可选和可调功能的串行通信协议的集成电路。还提供了用于设计这种电路的工具。该协议支持不同的数据传输模式，如流数据和分组数据。可以提供常规数据端口和优先级数据端口，使得优先级数据可以在传输期间嵌套在常规数据内。可以提供各种级别的数据完整性保护。如果不需要数据完整性保护，用户可以选择从给定的集成电路设计中省略数据完整性保护，从而节省资源。如果需要数据完整性保护，用户可以从不同的可用级别选择数据完整性保护。可以使用用户定义的数据信道来复用数据。

9. 发明授权

US08406258B1 Apparatus and methods for low-jitter transceiver clocking 有权
标题翻译：低抖动收发器时钟的装置和方法
公开(公告)号：US08406258B1
公开(公告)日：2013-03-26
申请号：US12752984
申请日：2010-04-01
申请人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
发明人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
IPC分类号： H04J3/06
CPC分类号： H03M9/00 , H03K19/1776 , H04J3/047 , H04J3/0685
摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。还公开了其它实施例和特征。

10. 发明授权

US08299802B2 Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics 有权
标题翻译：使用动态模拟测试多路复用器对系统中的模拟信号进行数字化的方法进行诊断
公开(公告)号：US08299802B2
公开(公告)日：2012-10-30
申请号：US12263290
申请日：2008-10-31
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev
IPC分类号： G01R31/02
CPC分类号： G01R31/3167
摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.
摘要翻译：提出了一种能够监视模拟模块内的模拟电压的集成电路。集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

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