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41. 发明授权

US08837237B2 Dual function compatible non-volatile memory device 有权
标题翻译：双功能兼容的非易失性存储设备
公开(公告)号：US08837237B2
公开(公告)日：2014-09-16
申请号：US14026359
申请日：2013-09-13
申请人： MOSAID Technologies Incorporated
发明人： Jin-Ki Kim
IPC分类号： G11C7/00 , G11C16/20 , G11C5/14 , G11C16/06 , G11C7/20
CPC分类号： G11C16/06 , G11C5/14 , G11C5/143 , G11C7/20 , G11C16/20
摘要： A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
摘要翻译：兼容异步操作和同步串行操作的双功能存储器件架构。双功能存储设备架构包括具有两个不同功能分配的一组物理端口。存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

42. 发明授权

US08825939B2 Semiconductor memory device suitable for interconnection in a ring topology 有权
标题翻译：适用于环形拓扑互连的半导体存储器件
公开(公告)号：US08825939B2
公开(公告)日：2014-09-02
申请号：US12141384
申请日：2008-06-18
申请人： HakJune Oh , Jin-Ki Kim
发明人： HakJune Oh , Jin-Ki Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C16/10 , G06F13/4239 , G11C7/10 , G11C7/1003
摘要： A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.
摘要翻译：一种半导体存储器件，包括：存储器; 用于接收命令锁存使能信号，地址锁存使能信号，信息信号和指示存储器件是否被控制器选择的选择信号的多个输入; 多个输出，用于向下一个装置释放一组输出信号; 控制电路; 和旁路电路。当选择信号指示由控制器选择的存储器件时，控制电路被配置为基于命令锁存使能信号和地址锁存使能信号来解释信息信号。当选择信号指示存储器件未被控制器选择时，旁路电路被配置为将命令锁存使能信号，地址锁存使能信号和信息信号传送到存储器件的输出。

43. 发明申请

US20140233325A1 DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 有权
标题翻译：具有完全独立部分阵列刷新功能的动态随机访问记忆
公开(公告)号：US20140233325A1
公开(公告)日：2014-08-21
申请号：US14265852
申请日：2014-04-30
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Jin-Ki KIM , HakJune OH
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
摘要翻译：动态随机存取存储器件包括多个存储器子块。每个子块具有连接多个数据存储单元的多个字线。部分阵列自刷新（PASR）配置设置是独立制作的。根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。可以选择子块地址的任何种类的组合。因此，存储器子块被完全独立地刷新。用于数据保留的用户可选择的存储器阵列提供有效的存储器控制编程，特别是对于低功率

44. 发明授权

US08782590B2 Power managers for an integrated circuit 有权
公开(公告)号：US08782590B2
公开(公告)日：2014-07-15
申请号：US13164362
申请日：2011-06-20
申请人： Barry Alan Hoberman , Daniel L. Hillman , Jon Shiell
发明人： Barry Alan Hoberman , Daniel L. Hillman , Jon Shiell
IPC分类号： H02J1/00 , G06F17/50
CPC分类号： H03K3/012 , G06F1/3203 , G06F1/324 , G06F1/3296 , H01L2924/00 , H01L2924/0002 , H02J4/00 , Y02D10/126 , Y02D10/172 , Y02D50/20 , Y10T307/406 , Y10T307/414
摘要： A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

45. 发明授权

US08743610B2 Method and system for accessing a flash memory device 有权
标题翻译：用于访问闪存设备的方法和系统
公开(公告)号：US08743610B2
公开(公告)日：2014-06-03
申请号：US13171667
申请日：2011-06-29
申请人： Jin-Ki Kim , Hong Beom Pyeon
发明人： Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： G11C16/00
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
摘要翻译：公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

46. 发明授权

US08737105B2 Bridge device architecture for connecting discrete memory devices to a system 有权
标题翻译：用于将分立存储器件连接到系统的桥接器件架构
公开(公告)号：US08737105B2
公开(公告)日：2014-05-27
申请号：US13091465
申请日：2011-04-21
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C5/02
CPC分类号： G11C7/00 , G11C5/02 , G11C5/025
摘要： Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.
摘要翻译：公开了用于连接分立存储器件的桥接器件架构。桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。桥接器件包括连接到至少一个分立存储器件的本地控制接口，连接到至少一个分立存储器件的本地输入/输出接口以及插入在本地控制接口和本地之间的全局输入/输出接口输入/输出接口。全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

47. 发明申请

US20210142857A1 METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE 有权
公开(公告)号：US20210142857A1
公开(公告)日：2021-05-13
申请号：US17154241
申请日：2021-01-21
申请人： Conversant Intellectual Property Management Inc.
发明人： Chung-Zen CHEN , Yang-Chieh LIN , Chung-Shan KUO
IPC分类号： G11C16/14 , G11C16/16 , G11C16/08 , G11C16/02 , G11C16/04
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

48. 发明申请

US20210132799A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
公开(公告)号：US20210132799A1
公开(公告)日：2021-05-06
申请号：US16950204
申请日：2020-11-17
申请人： Conversant Intellectual Property Management Inc.
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G06F3/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C16/10 , G11C16/28 , G11C16/32 , G11C16/04 , G11C14/00
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

49. 发明授权

US10998048B2 Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices 有权
公开(公告)号：US10998048B2
公开(公告)日：2021-05-04
申请号：US16580099
申请日：2019-09-24
申请人： Conversant Intellectual Property Management Inc.
发明人： Hyoung Seub Rhie
IPC分类号： G11C16/14 , G11C16/06
摘要： A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

50. 发明申请

US20210036689A1 POWER MANAGERS FOR AN INTEGRATED CIRCUIT 有权
公开(公告)号：US20210036689A1
公开(公告)日：2021-02-04
申请号：US16928311
申请日：2020-07-14
申请人： Conversant Intellectual Property Management Inc.
发明人： Barry Alan HOBERMAN , Daniel L. HILLMAN , Jon Shiell
IPC分类号： H03K3/012 , G06F1/3203 , G06F1/324 , G06F1/3296 , H02J4/00
摘要： Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.

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