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1. 发明授权

US11600323B2 Non-volatile memory device with concurrent bank operations 有权
公开(公告)号：US11600323B2
公开(公告)日：2023-03-07
申请号：US17246190
申请日：2021-04-30
申请人： Mosaid Technologies Incorporated
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C11/56 , G11C7/10 , G11C16/10 , G11C16/26 , G06F1/12 , G11C16/16 , G11C16/34 , G11C16/06
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

2. 发明授权

US11594281B2 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权
公开(公告)号：US11594281B2
公开(公告)日：2023-02-28
申请号：US17154241
申请日：2021-01-21
申请人： Mosaid Technologies Incorporated
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/14 , G11C16/16 , G11C16/08 , G11C16/02 , G11C16/04
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

3. 发明申请

US20230046725A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
公开(公告)号：US20230046725A1
公开(公告)日：2023-02-16
申请号：US17731408
申请日：2022-04-28
申请人： Mosaid Technologies Incorporated
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G06F3/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C16/10 , G11C16/28 , G11C16/32 , G11C16/04 , G11C14/00
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

4. 发明授权

US09070461B2 NAND flash memory having multiple cell substrates 有权
标题翻译： NAND闪存具有多个单元基板
公开(公告)号：US09070461B2
公开(公告)日：2015-06-30
申请号：US14032816
申请日：2013-09-20
申请人： MOSAID Technologies Incorporated
发明人： Jin-Ki Kim
IPC分类号： G11C11/34 , G11C16/16 , H01L27/115
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11524
摘要： A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
摘要翻译：具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。当井区的面积减小时，每个井区的电容相应减小。因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

5. 发明申请

US20150092494A1 Vertical Gate Stacked NAND and Row Decoder for Erase Operation 有权
标题翻译：垂直门堆叠NAND和行解码器，用于擦除操作
公开(公告)号：US20150092494A1
公开(公告)日：2015-04-02
申请号：US14044449
申请日：2013-10-02
申请人： Mosaid Technologies Incorporated
发明人： Hyoung Seub Rhie
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14
摘要： A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.
摘要翻译：三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压以及对阵列中的位线结构的高通电压。

6. 发明授权

US08902910B2 Ring-of-clusters network topologies 有权
标题翻译：集群网络拓扑结构
公开(公告)号：US08902910B2
公开(公告)日：2014-12-02
申请号：US14057102
申请日：2013-10-18
申请人： MOSAID Technologies Incorporated
发明人： Steven Przybylski
IPC分类号： H04L12/28 , G06F13/42 , H04L12/46 , H04L12/42
CPC分类号： H04L12/4637 , G06F13/4243 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H04L12/42 , Y02D10/14 , Y02D10/151 , H01L2224/32225 , H01L2924/00012
摘要： In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.
摘要翻译：在集群中的网络拓扑结构中，并行访问从属设备组，使得环周围的延迟与集群的数量成比例，与集成电路的数量成正比。集群的设备共享输入和输出环段，使得到达输入段的数据包被集群中的所有设备接收和解释。在其他实施例中，每个群集中的一个或全部除了一个从设备是睡着的或者被禁用的，使得它们不输入和解释传入的分组。无论如何，在所有实施例中，集群的从站可能在控制器的方向下协作，以确保其中至少一个在任何给定时间主动地驱动输出段。可以通过设备ID，集群ID或其组合来寻址设备。本发明的实施例适用于利用多芯片模块实现和垂直电路堆叠的形式。

7. 发明授权

US08879311B2 Phase change memory word line driver 有权
标题翻译：相变存储器字线驱动器
公开(公告)号：US08879311B2
公开(公告)日：2014-11-04
申请号：US13973600
申请日：2013-08-22
申请人： Mosaid Technologies Incorporated
发明人： Hong Beom Pyeon
IPC分类号： G11C11/00 , G11C13/00 , G11C8/08 , G11C8/14
CPC分类号： G11C13/0069 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C2013/0071
摘要： A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.
摘要翻译：一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

8. 发明授权

US08873366B2 Frequency division multiplexing system with selectable rate 有权
标题翻译：频分复用系统，可选速率
公开(公告)号：US08873366B2
公开(公告)日：2014-10-28
申请号：US14157824
申请日：2014-01-17
申请人： MOSAID Technologies Incorporated
发明人： D. J. Richard Van Nee
IPC分类号： H04J11/00
CPC分类号： H04L27/2602 , H04L1/0002 , H04L5/1446 , H04L25/08 , H04L27/2605 , H04L27/2607 , H04L27/2647 , H04L27/2662
摘要： An OFDM system uses a normal mode which has a symbol length T, a guard time TG and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KTG where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.
摘要翻译： OFDM系统使用具有在时间T上是正交的符号长度T，保护时间TG和一组N个子载波的正常模式，以及具有符号长度KT和保护时间KTG的一个或多个回退模式其中K是大于1的整数。相同的一组N个子载波用于回退模式，与正常模式一样。由于使用相同的子载波集合，所以总带宽基本上是恒定的，所以别名滤波不需要是自适应的。傅里叶变换操作与正常模式相同。因此，回退模式的硬件成本很低。在回退模式中，增加的保护时间提供更好的延迟扩展容限，并且增加的符号长度提供改善的信噪比性能，并因此提高范围，以降低的数据速率为代价。

9. 发明授权

US08837655B2 Memory controller with flexible data alignment to clock 有权
标题翻译：内存控制器与时钟灵活的数据对齐
公开(公告)号：US08837655B2
公开(公告)日：2014-09-16
申请号：US13887937
申请日：2013-05-06
申请人： Mosaid Technologies Incorporated
发明人： Hong Beom Pyeon
IPC分类号： H04L7/00 , G11C7/10 , G11C5/02 , G11C7/20 , G11C7/22 , G11C7/02 , H01L25/065
CPC分类号： G06F1/10 , G11C5/025 , G11C7/02 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/20 , G11C7/22 , G11C7/222 , H01L25/0657 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H04L7/0008 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.
摘要翻译：系统包括存储器控制器和与存储器控制器串联连接的多个存储器件。系统操作与以源同步时钟结构的方式提供的时钟同步。源同步时钟结构包括一个PLL（锁相环），其重新形成输入时钟，并提供重构时钟。 PLL提供90°相位的移位时钟。相移时钟和数据从第一设备发送到第二设备。时钟相移提供了要传输数据的中心边沿时钟。设备被分配唯一的ID。最后一个设备的ID号码的最低有效位用于确定时钟对准：边沿或中心对齐时钟与存储器控制器产生的数据。

10. 发明授权

US08806305B2 Error detection and correction codes for channels and memories with incomplete error characteristics 有权
标题翻译：具有不完整误差特性的通道和存储器的错误检测和纠正码
公开(公告)号：US08806305B2
公开(公告)日：2014-08-12
申请号：US13865514
申请日：2013-04-18
申请人： MOSAID Technologies Incorporated
发明人： Steven Przybylski
IPC分类号： H03M13/00
CPC分类号： G11C29/00 , G06F11/1072 , H03M13/036 , H03M13/353 , H03M13/49
摘要： A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.
摘要翻译：通道具有第一和第二端。信道的第一端耦合到发射机。信道能够发送从从第一端到第二端的符号集中选择的符号。该通道显示不完整的错误引入属性。代码包括一组代码字。代码字集合的元素是一个或多个代码符号。代码符号是符号集的成员。根据信道的误差引入属性，码集集合的元素之间的最小修改汉明距离大于码集集合元素之间的最小汉明距离。还描述了存储器件，使用该通道的方法以及生成代码的方法。

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