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41. 发明授权

US08492195B2 Method for forming stackable non-volatile resistive switching memory devices 有权
标题翻译：用于形成可堆叠的非易失性电阻式开关存储器件的方法
公开(公告)号：US08492195B2
公开(公告)日：2013-07-23
申请号：US12861650
申请日：2010-08-23
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L21/06
CPC分类号： H01L27/2463 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/148 , H01L45/16
摘要： A method for forming a vertically stacked memory device includes forming a first dielectric material overlying a surface region of a semiconductor substrate, forming first memory cells overlying the first dielectric material including a first top metal wiring spatially extending in a first direction, a first bottom metal wiring spatially extending in a second direction orthogonal to the first direction, and first switching elements sandwiched in intersection regions between the first top metal wiring and the first bottom metal wiring, forming a second dielectric material overlying the first top metal wiring, forming second memory cells overlying the second dielectric material including a second top metal wiring extending in the first direction, a second bottom wiring spatially extending in the second direction, and second switching elements sandwiched in intersection regions of the second top metal wiring and the second bottom metal wiring.
摘要翻译：一种用于形成垂直堆叠的存储器件的方法包括：形成覆盖在半导体衬底的表面区域上的第一电介质材料，形成覆盖第一电介质材料的第一存储单元，该第一存储单元包括沿第一方向空间延伸的第一顶金属布线，第一底金属在与第一方向正交的第二方向上空间延伸的布线，以及夹在第一顶金属布线和第一底金属布线之间的交叉区域中的第一开关元件，形成覆盖在第一顶金属布线上的第二电介质材料，形成第二存储单元覆盖包括在第一方向上延伸的第二顶部金属布线的第二介电材料，在第二方向上空间延伸的第二底部布线，以及夹在第二顶部金属布线和第二底部金属布线的交叉区域中的第二开关元件。

42. 发明授权

US08391049B2 Resistor structure for a non-volatile memory device and method 有权
公开(公告)号：US08391049B2
公开(公告)日：2013-03-05
申请号：US12894087
申请日：2010-09-29
申请人： Sung Hyun Jo
发明人： Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： H01L28/20 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/33 , G11C2213/56 , H01L27/2463 , H01L45/085 , H01L45/1253 , H01L45/1675
摘要： A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

43. 发明申请

US20130033923A1 CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR 有权
标题翻译：用于同时读取操作的电路及其方法
公开(公告)号：US20130033923A1
公开(公告)日：2013-02-07
申请号：US13651169
申请日：2012-10-12
申请人： Crossbar, Inc.
发明人： Harry KUO , Hagop NAZARIAN
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2207/005 , G11C2213/15 , G11C2213/78
摘要： A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.
摘要翻译：非易失性存储器件包括存储单元阵列，每个存储器单元具有电阻存储器单元和本地字线。每个存储单元具有第一端和第二端，第二端耦合到相应存储单元的本地字线。提供位线，每一个都连接到每个电阻存储器单元的第一端。提供了多个选择晶体管，每个选择晶体管与一个存储器单元相关联并且具有耦合到相关联的存储器单元的本地字线的漏极端子。提供第一和第二全局字线，每个字线耦合到至少一个选择晶体管的控制端。提供第一和第二源极线，每个耦合到至少一个选择晶体管的源极端子。存储器件被配置为在读取操作中同时读出一个选择的存储器单元中的所有电阻存储器单元。

44. 发明申请

US20130027081A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
标题翻译：现场可编程门阵列使用两端非易失性存储器
公开(公告)号：US20130027081A1
公开(公告)日：2013-01-31
申请号：US13194500
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177
CPC分类号： H03K19/0013 , G11C13/0002 , G11C13/004 , G11C13/0069 , H03K19/0944 , H03K19/1776 , H03K19/17764 , H03K19/17776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。

45. 发明申请

US20130027079A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
公开(公告)号：US20130027079A1
公开(公告)日：2013-01-31
申请号：US13194479
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/177 , G11C11/00 , H01L21/82
CPC分类号： H03K19/17776 , G11C13/0021 , H01L27/101 , H03K19/0013 , H03K19/00315 , H03K19/0944 , H03K19/1776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

46. 发明授权

US08315079B2 Circuit for concurrent read operation and method therefor 有权
标题翻译：并行读取操作电路及其方法
公开(公告)号：US08315079B2
公开(公告)日：2012-11-20
申请号：US12900232
申请日：2010-10-07
申请人： Harry Kuo , Hagop Nazarian
发明人： Harry Kuo , Hagop Nazarian
IPC分类号： G11C7/06
CPC分类号： G11C13/0004 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2207/005 , G11C2213/15 , G11C2213/78
摘要： A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.
摘要翻译：非易失性存储器件包括存储单元阵列，每个存储器单元具有电阻存储器单元和本地字线。每个存储单元具有第一端和第二端，第二端耦合到相应存储单元的本地字线。提供位线，每一个都连接到每个电阻存储器单元的第一端。提供了多个选择晶体管，每个选择晶体管与一个存储器单元相关联并且具有耦合到相关联的存储器单元的本地字线的漏极端子。提供第一和第二全局字线，每个字线耦合到至少一个选择晶体管的控制端。提供第一和第二源极线，每个耦合到至少一个选择晶体管的源极端子。存储器件被配置为在读取操作中同时读出一个选择的存储器单元中的所有电阻存储器单元。

47. 发明授权

US08274812B2 Write and erase scheme for resistive memory device 有权
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：US08274812B2
公开(公告)日：2012-09-25
申请号：US12815369
申请日：2010-06-14
申请人： Hagop Nazarian , Sung Hyun Jo
发明人： Hagop Nazarian , Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

48. 发明申请

US20120187364A1 ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD 有权
标题翻译：非易失性存储器件的ON / OFF比率和方法
公开(公告)号：US20120187364A1
公开(公告)日：2012-07-26
申请号：US13436714
申请日：2012-03-30
申请人： Scott Brad HERNER
发明人： Scott Brad HERNER
IPC分类号： H01L27/24
CPC分类号： H01L45/1273 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/16 , H01L45/1675
摘要： A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element.
摘要翻译：开关器件包括形成在衬底上的第一电介质材料。顺序地形成底部布线材料和开关材料，覆盖在第一介电材料上。底部布线材料和开关材料被图案化和蚀刻以形成具有顶表面区域和侧面区域的第一结构。第一结构包括底部布线结构和具有包括暴露区域的顶表面区域的开关元件。第二介电材料形成在第一结构上。第一开口区域形成在第二电介质层的一部分中以暴露顶表面区域的一部分。电介质侧壁结构形成在第一开口区域的侧面上。包括导电材料的顶部布线材料形成在顶表面区域上以与开关元件直接接触。

49. 发明授权

US08168506B2 On/off ratio for non-volatile memory device and method 有权
标题翻译：非易失性存储器件的开/关比和方法
公开(公告)号：US08168506B2
公开(公告)日：2012-05-01
申请号：US12835699
申请日：2010-07-13
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L21/20
CPC分类号： H01L45/1273 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/16 , H01L45/1675
摘要： This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying at lease the top surface region of the switching element such that the conductive material is in direct contact with the switching element. The side wall spacer reduces a contact area for the switching element and the conductive material and thus a reduced active device area for the switching device. In a specific embodiment, the reduced area provides for an increase in device ON/OFF current ratio.
摘要翻译：该应用描述了形成开关器件的方法。该方法包括形成覆盖在衬底的表面区域上的第一电介质材料。底部布线材料形成在第一介电材料上方，并且覆盖在底部布线材料上的开关材料沉积。对底部布线材料和开关材料进行第一图案化和蚀刻工艺以形成具有顶表面区域和侧面区域的第一结构。第一结构至少包括底部布线结构和具有包括开关元件的暴露区域的顶表面区域的开关元件。至少形成包括开关元件的暴露区域的第一结构的第二电介质材料。该方法在第二电介质层的一部分中形成第一开口区域以暴露开关元件的顶表面区域的一部分。电介质侧壁结构形成在第一开口区域的侧面上。包括导电材料的顶部布线材料形成为覆盖开关元件的顶表面区域，使得导电材料与开关元件直接接触。侧壁间隔物减少了开关元件和导电材料的接触面积，并因此降低了用于开关器件的有源器件面积。在具体实施例中，减小的面积提供了器件ON / OFF电流比的增加。

50. 发明申请

US20210280246A1 SELECTOR DEVICE FOR TWO-TERMINAL MEMORY 有权
公开(公告)号：US20210280246A1
公开(公告)日：2021-09-09
申请号：US17214162
申请日：2021-03-26
申请人： CROSSBAR, INC.
发明人： Sung Hyun JO
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00 , G11C11/56 , G11C11/16
摘要： Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

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