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1. 发明授权

US08796658B1 Filamentary based non-volatile resistive memory device and method 有权
标题翻译：基于长丝的非易失性电阻式存储器件及方法
公开(公告)号：US08796658B1
公开(公告)日：2014-08-05
申请号：US13466008
申请日：2012-05-07
申请人： Hagop Nazarian , Sung Hyun Jo
发明人： Hagop Nazarian , Sung Hyun Jo
IPC分类号： H01L47/00 , H01L27/24 , H01L45/00
CPC分类号： H01L45/1641 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/148 , H01L45/165 , H01L45/1675
摘要： A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.
摘要翻译：电阻式存储器件包括包含正金属离子源的第一金属层，具有上表面和下表面的开关介质，其中上表面与第一金属层相邻，其中开关介质包括包含正极的导电细丝从上表面朝向下表面形成的正金属离子源的金属离子，半导体衬底，设置在半导体衬底上方的第二金属层，设置在第二金属层上方的非金属导电层，以及界面区域在非金属导电层和具有负离子电荷的开关介质之间。

2. 发明授权

US08723154B2 Integration of an amorphous silicon resistive switching device 有权
标题翻译：集成非晶硅电阻开关器件
公开(公告)号：US08723154B2
公开(公告)日：2014-05-13
申请号：US12894057
申请日：2010-09-29
申请人： Sung Hyun Jo , Hagop Nazarian
发明人： Sung Hyun Jo , Hagop Nazarian
IPC分类号： H01L29/12 , H01L29/8605 , H01L27/105 , H01L21/8239
CPC分类号： H01L45/1233 , H01L27/2436 , H01L45/085 , H01L45/1266 , H01L45/148 , H01L45/1616 , H01L45/1675 , H01L45/1683
摘要： An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device.
摘要翻译：集成电路器件。集成电路器件包括具有表面区域的半导体衬底。栅极电介质层覆盖在衬底的表面区域上。该器件包括具有p +有源区的MOS器件。 p +有源区形成用于电阻式开关器件的第一电极。电阻开关器件包括覆盖p +有源区的非晶硅开关材料和覆盖在第一金属导体结构上的金属电极。金属电极包括金属材料，当对金属电极施加正偏压时，在非晶硅开关材料中形成金属区域。 MOS器件为集成电路器件提供选择晶体管。

3. 发明申请

US20130024742A1 ERROR CORRECTION FOR FLASH MEMORY 有权
标题翻译： FLASH存储器的错误校正
公开(公告)号：US20130024742A1
公开(公告)日：2013-01-24
申请号：US13616379
申请日：2012-09-14
申请人： Hagop Nazarian , Ping Hou
发明人： Hagop Nazarian , Ping Hou
IPC分类号： H03M13/29
CPC分类号： G06F11/1072 , G11C2029/0411
摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.
摘要翻译：本文描述了提供电子存储器的单位和多位纠错。作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。可疑区域可以定义分布的潜在错误位。如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

4. 发明申请

US20120327717A1 HIGH READ SPEED MEMORY WITH GATE ISOLATION 有权
标题翻译：高速读存储器与门隔离
公开(公告)号：US20120327717A1
公开(公告)日：2012-12-27
申请号：US13600527
申请日：2012-08-31
申请人： Richard Fastow , Hagop Nazarian , Lei Xue
发明人： Richard Fastow , Hagop Nazarian , Lei Xue
IPC分类号： G11C16/26 , H01L27/088 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/063 , H01L27/0207 , H01L27/11529 , H01L27/11573
摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.
摘要翻译：本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

5. 发明申请

US20120236650A1 NAND ARCHTECTURE INCLUDING RESITIVE MEMORY CELLS 有权
标题翻译： NAND存储器包括可记忆存储器
公开(公告)号：US20120236650A1
公开(公告)日：2012-09-20
申请号：US13051296
申请日：2011-03-18
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： G11C16/04 , G11C11/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C16/0483 , G11C2213/33 , G11C2213/53 , G11C2213/56 , G11C2213/75
摘要： A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells.
摘要翻译：非易失性存储器件包括第一选择晶体管，第二选择晶体管和设置在第一和第二选择晶体管之间的第一存储单元串。每个第一存储单元具有第一电阻存储单元和第一晶体管。第一电阻存储单元与第一晶体管的栅极串联。非易失性存储器件还包括耦合到第一选择晶体管的漏极和多个字线的第一位线。每个字线耦合到第一存储器单元之一。

6. 发明申请

US20110317466A1 HIGH READ SPEED MEMORY WITH GATE ISOLATION 有权
标题翻译：高速读存储器与门隔离
公开(公告)号：US20110317466A1
公开(公告)日：2011-12-29
申请号：US12824352
申请日：2010-06-28
申请人： Richard Fastow , Hagop Nazarian , Lei Xue
发明人： Richard Fastow , Hagop Nazarian , Lei Xue
IPC分类号： G11C5/06 , H01L21/82
CPC分类号： G11C16/0483 , G11C5/063 , H01L27/0207 , H01L27/11529 , H01L27/11573
摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.
摘要翻译：本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

7. 发明申请

US20110305066A1 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：US20110305066A1
公开(公告)日：2011-12-15
申请号：US12815369
申请日：2010-06-14
申请人： Hagop NAZARIAN , Sung Hyun Jo
发明人： Hagop NAZARIAN , Sung Hyun Jo
IPC分类号： G11C11/00 , G01R31/28
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

8. 发明申请

US20090109758A1 NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE 有权
标题翻译：非易失性存储器阵列分区结构和使用单层电池和多级电池在方法中的方法
公开(公告)号：US20090109758A1
公开(公告)日：2009-04-30
申请号：US11929761
申请日：2007-10-30
申请人： Hagop Nazarian , Michael Achter , Harry Kuo
发明人： Hagop Nazarian , Michael Achter , Harry Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0491
摘要： A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.
摘要翻译：一种包括程序组件的系统，该程序组件使用FN隧道对一组或多个NVM单元阵列的一个或多个非易失性存储器（“NVM”）单元进行编程，所述擦除组件擦除所述NVM单元阵列的一对或多个NVM单元使用FN隧道的NVM单元，以及读取组件，其读取NVM单元阵列阵列中的一个或多个NVM单元。

9. 发明申请

US20080225596A1 HIGH ACCURACY ADAPTIVE PROGRAMMING 有权
标题翻译：高精度自适应编程
公开(公告)号：US20080225596A1
公开(公告)日：2008-09-18
申请号：US11687492
申请日：2007-03-16
申请人： Michael Achter , Hagop Nazarian
发明人： Michael Achter , Hagop Nazarian
IPC分类号： G11C7/00
CPC分类号： G11C16/10
摘要： Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.
摘要翻译：闪存设备具有可被擦除和编程的多个存储器单元。执行电压验证检查允许将适当的状态变化电压施加到闪存器件。通过访问查找表来确定适当的状态变化电压。使用适当的状态变化电压允许电池在更多的总体编程周期下运行。

10. 发明申请

US20070030739A1 Method of comparison between cache and data register for non-volatile memory 有权
标题翻译：用于非易失性存储器的缓存和数据寄存器之间的比较方法
公开(公告)号：US20070030739A1
公开(公告)日：2007-02-08
申请号：US11580660
申请日：2006-10-13
申请人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop Nazarian
发明人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop Nazarian
IPC分类号： G11C7/06
CPC分类号： G11C7/22 , G06F12/0893 , G11C16/3436 , G11C2207/2245 , G11C2216/14
摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.
摘要翻译：描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较数据位并产生指示数据匹配或不匹配的信号标志。这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或结果逻辑组合以指示完整数据块的匹配或不匹配。

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