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41. 发明授权

US08174892B2 Increased NAND flash memory read throughput 有权
标题翻译：增加NAND闪存读取吞吐量
公开(公告)号：US08174892B2
公开(公告)日：2012-05-08
申请号：US13042071
申请日：2011-03-07
申请人： Dzung H. Nguyen , Frankie F. Roohparvar
发明人： Dzung H. Nguyen , Frankie F. Roohparvar
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
摘要翻译：从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页。来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。

42. 发明授权

US08164375B2 Delay line synchronizer apparatus and method 有权
标题翻译：延迟线同步装置及方法
公开(公告)号：US08164375B2
公开(公告)日：2012-04-24
申请号：US12568525
申请日：2009-09-28
申请人： Paul A. LaBerge
发明人： Paul A. LaBerge
IPC分类号： H03K3/00
CPC分类号： G06F1/12
摘要： A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
摘要翻译：同步器系统和方法可以与传统的可调节延迟电路一起使用，以便在输出时钟信号之一的可调节延迟电路的时间延迟被改变时，保持不同时钟域的时钟信号之间的伪同步相位关系。

43. 发明授权

US08164132B2 Methods of forming integrated circuit devices 有权
标题翻译：形成集成电路器件的方法
公开(公告)号：US08164132B2
公开(公告)日：2012-04-24
申请号：US13073490
申请日：2011-03-28
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
摘要翻译：本发明包括形成半导体结构的方法和形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电材料以形成电容器电极结构。形成与至少一些电极结构物理接触的晶格，在晶格上形成保护帽，随后去除一些绝缘材料以暴露电极结构的外表面。晶格可以减轻电极结构的结构完整性的倾倒或其它损失，并且保护帽可以保护绝缘材料的被覆盖部分免受蚀刻。在电极结构的外侧壁露出之后，去除保护盖。然后将电极结构并入电容器结构。

44. 发明授权

US08154932B2 Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory 有权
标题翻译：通过在写入地址被提供给存储器的时间和向存储器提供写入数据的时间之间选择性地引入相对延迟来提高存储器访问的效率
公开(公告)号：US08154932B2
公开(公告)日：2012-04-10
申请号：US13051038
申请日：2011-03-18
申请人： J. Thomas Pawlowski
发明人： J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F12/0207 , G06F12/0607 , G11C7/1039 , G11C7/1072 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.
摘要翻译：提供了用于减少多组存储器件中的连续写入和读取访问之间的延迟的系统和方法。计算机电路修改写访问的地址和数据之间的相对定时，减少连续写入和读取访问之间的延迟。与这些计算机电路接口的存储器件使用发布的写入访问，以在处理写入访问之前有效地将修改的相对定时返回到其原始时序。

45. 发明授权

US08154126B2 Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods 有权
标题翻译：用于通过这些方法形成的微电子器件和微电子器件的晶片级封装的方法
公开(公告)号：US08154126B2
公开(公告)日：2012-04-10
申请号：US12834125
申请日：2010-07-12
申请人： James L. Voelz
发明人： James L. Voelz
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/48 , H01L21/56 , H01L21/561 , H01L23/3114 , H01L23/562 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/24227 , H01L2224/274 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要： Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices re disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state.
摘要翻译：用于封装微电子器件的方法，具有封装管芯的微电子工件和本文公开的微电子器件。本发明的一个方面涉及一种包括具有器件侧和背面的衬底的微电子工件。在一个实施例中，微电子工件还包括形成在衬底的器件侧上的多个管芯，在管芯上方的电介质层，以及介电层上的多个接合焊盘。所述管芯具有集成电路和电耦合到所述集成电路的多个接合焊盘。球垫布置在衬底上相应的模具上的球垫阵列中。本实施例的微电子工件还包括在衬底背面上的保护层。保护层由处于可流动状态的材料形成在基板的背面，然后固化到不可流动的状态。

46. 发明授权

US08127081B2 Memory hub and access method having internal prefetch buffers 有权
标题翻译：具有内部预取缓冲区的内存集线器和访问方法
公开(公告)号：US08127081B2
公开(公告)日：2012-02-28
申请号：US12185615
申请日：2008-08-04
申请人： Terry R. Lee , Joseph Jeddeloh
发明人： Terry R. Lee , Joseph Jeddeloh
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024 , G06F2212/6026
摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
摘要翻译：存储器模块包括耦合到多个存储器件的存储器集线器。存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。标签逻辑存储与预取数据的地址对应的预取地址。标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。如果是，则从预取缓冲器读取所请求的数据。否则，从存储器件读取所请求的数据。

47. 发明申请

US20120039123A1 MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件中的多级编程
公开(公告)号：US20120039123A1
公开(公告)日：2012-02-16
申请号：US13279717
申请日：2011-10-24
申请人： Hagop A. Nazarian
发明人： Hagop A. Nazarian
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C2211/5648
摘要： The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.
摘要翻译：本发明的编程方法通过在具有最高阈值电压的逻辑状态的同一字线上最初编程单元来最小化程序干扰。字线上的剩余单元按照降低阈值电压电平的顺序被编程到它们各自的逻辑状态。

48. 发明申请

US20120033513A1 DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES 失效
标题翻译：分布式写入数据驱动器，用于冲突访问记忆
公开(公告)号：US20120033513A1
公开(公告)日：2012-02-09
申请号：US13275568
申请日：2011-10-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C8/18
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读命令每次突发存取发出一次，消除了周期频率下的切换读控制线。控制线转换终止访问并初始化另一个突发访问。

49. 发明授权

US08107304B2 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US08107304B2
公开(公告)日：2012-01-31
申请号：US12642414
申请日：2009-12-18
申请人： Todd A. Merritt , Troy A. Manning
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/407
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。控制线转换终止访问并初始化另一个突发访问。写周期时间最大化，从而允许突发模式工作频率的增加。读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

50. 发明授权

US08098508B2 Configurable inputs and outputs for memory stacking system and method 有权
标题翻译：用于内存堆叠系统和方法的可配置输入和输出
公开(公告)号：US08098508B2
公开(公告)日：2012-01-17
申请号：US12559373
申请日：2009-09-14
申请人： Jeffery W Janzen
发明人： Jeffery W Janzen
IPC分类号： G11C5/06
CPC分类号： G11C7/1078 , G11C5/02 , G11C5/04 , G11C7/109 , G11C7/22 , G11C7/225 , G11C11/4093 , G11C11/4096 , G11C2207/2254 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01055
摘要： Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.
摘要翻译：本发明的实施例涉及用于存储器和存储器堆叠应用的可配置输入和/或输出。更具体地，本发明的实施例包括存储器件，其包括具有配置为通过特定信号实现的电路的管芯，被配置为接收特定信号的输入引脚，以及路径选择器，其被配置为选择性地指定到电路的信号路径从输入引脚。

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