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1. 发明申请

US20180107597A1 MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开
公开(公告)号：US20180107597A1
公开(公告)日：2018-04-19
申请号：US15653990
申请日：2017-07-19
申请人： SK hynix Inc.
发明人： Sang-Gu JO , Yong-Ju KIM
IPC分类号： G06F12/0804 , G06F13/16 , G11C29/44 , G06F12/06 , G11C11/34 , G11C11/407
CPC分类号： G06F12/0804 , G06F12/06 , G06F13/1647 , G06F13/1668 , G11C11/34 , G11C11/407 , G11C29/4401 , G11C29/72 , G11C29/83
摘要： A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

2. 发明授权

US09922711B2 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating 有权
公开(公告)号：US09922711B2
公开(公告)日：2018-03-20
申请号：US15499519
申请日：2017-04-27
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C14/00 , G11C13/00 , H01L27/108 , H01L27/24 , H01L29/78 , H01L45/00
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

3. 发明申请

US20180010968A1 SEMICONDUCTOR DEVICE HAVING TEMPERATURE SENSOR CIRCUIT THAT DETECTS A TEMPERATURE RANGE UPPER LIMIT VALUE AND A TEMPERATURE RANGE LOWER LIMIT VALUE 有权
公开(公告)号：US20180010968A1
公开(公告)日：2018-01-11
申请号：US15713643
申请日：2017-09-23
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G01K7/16 , H03K17/687 , H03K17/22 , H03K17/14 , H03K3/012 , G11C11/4096 , G11C11/4093 , G11C11/4074 , G11C11/407 , G11C11/406 , G11C7/04 , G11C7/00 , G01K13/00 , G01K7/01 , G01K7/00 , G01K3/00 , H03K21/10
CPC分类号： G01K7/16 , G01K3/005 , G01K7/00 , G01K7/01 , G01K13/00 , G11C7/00 , G11C7/04 , G11C11/40626 , G11C11/407 , G11C11/4074 , G11C11/4093 , G11C11/4096 , H03K3/012 , H03K17/145 , H03K17/223 , H03K17/687 , H03K21/10 , Y10T307/773
摘要： A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

4. 发明授权

US09831247B2 Memory device comprising electrically floating body transistor 有权
公开(公告)号：US09831247B2
公开(公告)日：2017-11-28
申请号：US15218287
申请日：2016-07-25
申请人： Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Yuniarto Widjaja
IPC分类号： H01L29/00 , H01L27/108 , H01L29/78 , G11C16/00 , G11C16/04 , H01L29/06 , G11C11/404 , G11C11/407
CPC分类号： H01L27/10802 , G11C11/404 , G11C11/407 , G11C16/00 , G11C16/0416 , H01L29/0649 , H01L29/7841
摘要： A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

5. 发明授权

US09631982B2 Semiconductor device having temperature sensor circuits 有权
公开(公告)号：US09631982B2
公开(公告)日：2017-04-25
申请号：US15049472
申请日：2016-02-22
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： H03K17/14 , G01K7/16 , G11C7/00 , G01K7/00 , G01K13/00 , H03K3/012 , H03K17/687 , G11C7/04 , G11C11/406 , H03K17/22 , H03K21/10 , G11C11/4074 , G11C11/4093 , G11C11/4096 , G11C11/407 , G01K7/01 , G01K3/00
CPC分类号： G01K7/16 , G01K3/005 , G01K7/00 , G01K7/01 , G01K13/00 , G11C7/00 , G11C7/04 , G11C11/40626 , G11C11/407 , G11C11/4074 , G11C11/4093 , G11C11/4096 , H03K3/012 , H03K17/145 , H03K17/223 , H03K17/687 , H03K21/10 , Y10T307/773
摘要： A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

6. 发明授权

US09412422B2 Memory device and method for putting a memory cell into a state with a reduced leakage current consumption 有权
标题翻译：用于将存储器单元置于具有降低的泄漏电流消耗的状态的存储器件和方法
公开(公告)号：US09412422B2
公开(公告)日：2016-08-09
申请号：US14338396
申请日：2014-07-23
申请人： Infineon Technologies AG
发明人： Peter Huber
IPC分类号： G11C5/14 , G11C11/407 , G11C11/417 , G11C11/408
CPC分类号： G11C5/14 , G11C11/407 , G11C11/4085 , G11C11/417
摘要： In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.
摘要翻译：在各种实施例中，存储器设备包括耦合到至少一个存储器单元的至少一个存储器单元和至少一个虚拟供电线。存储器件被设计成使得存在于虚拟电源线上的电压电位在通过存储在存储器件内的电荷在主存储器中被有效存取之后被改变，在主存储器期间，使得具有降低的泄漏电流消耗的存储器单元的状态得以实现。

7. 发明授权

US09401206B2 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating 有权
公开(公告)号：US09401206B2
公开(公告)日：2016-07-26
申请号：US14680268
申请日：2015-04-07
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C14/00 , G11C11/21 , G11C11/404 , G11C13/00 , H01L29/78 , H01L45/00 , H01L27/108 , G11C11/4072 , H01L27/24
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

8. 发明授权

US09349737B2 Passing access line structure in a memory device 有权
标题翻译：在存储设备中传递访问线路结构
公开(公告)号：US09349737B2
公开(公告)日：2016-05-24
申请号：US14511371
申请日：2014-10-10
申请人： Micron Technology, Inc.
发明人： Srinivas Pulugurtha , Sourabh Dhir , Rajesh N. Gupta , Sanh D. Tang , Si-Woo Lee , Haitao Liu
IPC分类号： H01L27/105 , H01L27/108 , G11C11/407
CPC分类号： H01L27/10826 , G11C7/02 , G11C11/407 , G11C11/4097 , H01L27/10879
摘要： A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.
摘要翻译：用于存储器件制造的方法包括在衬底上形成多个连续的翅片。在翅片周围形成绝缘体材料。将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。在翅片和绝缘体材料上形成金属。形成在暴露区域上的金属形成为比鳍片上方浅的深度。

9. 发明授权

US09263116B2 Memory device 有权
公开(公告)号：US09263116B2
公开(公告)日：2016-02-16
申请号：US14717071
申请日：2015-05-20
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Jun Koyama , Shunpei Yamazaki
IPC分类号： G11C11/24 , G11C11/407 , G11C5/02 , G11C11/404 , G11C11/4097 , G11C8/08
CPC分类号： G11C11/407 , G11C5/025 , G11C8/08 , G11C11/404 , G11C11/4097
摘要： In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.

10. 发明申请

US20150287452A1 DRAM SECURITY ERASE 有权
标题翻译： DRAM安全删除
公开(公告)号：US20150287452A1
公开(公告)日：2015-10-08
申请号：US14642588
申请日：2015-03-09
申请人： Tessera, Inc.
发明人： Michael C. Parris
IPC分类号： G11C11/4096 , G11C11/4091
CPC分类号： G11C11/4096 , G11C11/407 , G11C11/4072 , G11C11/4078 , G11C11/4091 , G11C11/4094
摘要： A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.
摘要翻译：存储器包括具有存储单元的DRAM阵列，耦合到存储器单元的字线和位线以及读出放大器。存储器可以被配置为执行其中DRAM阵列的字线被设置为活动状态的方法。当字线有效时，根据耦合到字线和相应位线的存储器单元之间的电荷流，在相应位线上产生信号。连接到相应位线的读出放大器可以保持不动，使得读出放大器不将信号放大到可存储的信号电平。然后，当字线再次设置为非活动状态时，不足的电荷残留在耦合到字线的存储器单元中，使得存储在耦合到字线的存储器单元中的数据被擦除。可以使用DRAM阵列的全部或选定范围的剩余数量的字线中的每一个来重复这些步骤，以便擦除存储在所有DRAM阵列中的数据或所选择的范围。

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