专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20160180951A1 MEASURING MEMORY WEAR AND DATA RETENTION INDIVIDUALLY BASED ON CELL VOLTAGE DISTRIBUTIONS 有权
标题翻译：基于单元电压分布测量记忆磨损和数据保持
公开(公告)号：US20160180951A1
公开(公告)日：2016-06-23
申请号：US14977143
申请日：2015-12-21
申请人： SanDisk Technologies Inc.
发明人： Neil Richard Darragh , Sergey Anatolievich Gorobets , Liam Michael Parker
IPC分类号： G11C16/34
CPC分类号： G06F3/0653 , G06F3/0625 , G06F3/0634 , G06F11/008 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/32 , G11C16/3418 , G11C16/3422 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/50004 , G11C29/52 , G11C29/56008 , G11C29/70 , G11C2029/5004
摘要： A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
摘要翻译：存储器系统或闪存卡可以包括用于存储器单元测量和分析的机制，其独立地测量/预测存储器磨损/耐久性，数据保持（DR），读取干扰和/或剩余余量。可以通过分析单元的各个电压电平的状态分布来独立地量化这些效应。特别地，可以分析存储器单元的单元电压分布的直方图以识别特定效果的签名（例如，磨损，DR，读取干扰，余量等）。这些测量可用于块循环，数据丢失预测或对存储器参数的调整。在适当的时间基于测量的优先行动可能会导致改进的内存管理和数据管理。该动作可以包括计算存储在存储器中的数据的剩余使用寿命，循环块，预测数据丢失，权衡或动态调整存储器参数。

42. 发明申请

US20160179113A1 Temperature Independent Reference Current Generation For Calibration 审中-公开
标题翻译：用于校准的温度独立参考电流产生
公开(公告)号：US20160179113A1
公开(公告)日：2016-06-23
申请号：US14928466
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Subodh Prakash Taigor , Sridhar Yadala , Rangarao Samineni
IPC分类号： G05F1/46
CPC分类号： G05F1/463 , G11C5/147 , G11C7/04 , G11C16/06 , G11C2207/2254 , H03K19/0005
摘要： Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be compared with a calibration current in a ZQ calibration circuit.
摘要翻译：本文公开了用于产生温度无关参考电流的技术，其可以在校准期间使用。可以基于通过片上校准电阻器的电流来产生不依赖于温度的参考电流。这减轻了对片外校准电阻器的需要，这可能是昂贵的并导致缓慢的校准。片上校准电阻器的一个端子处的电压可以被调制以基本上消除片上校准电阻器的温度系数。这可能导致电流通过片上校准电阻器与温度无关。温度独立参考电流可以与ZQ校准电路中的校准电流进行比较。

43. 发明申请

US20160172368A1 Contact For Vertical Memory With Dopant Diffusion Stopper And Associated Fabrication Method 有权
标题翻译：联系垂直记忆与掺杂剂扩散塞和相关制作方法
公开(公告)号：US20160172368A1
公开(公告)日：2016-06-16
申请号：US14572146
申请日：2014-12-16
申请人： SANDISK TECHNOLOGIES INC.
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L27/1052 , H01L27/1128 , H01L27/11524 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.
摘要翻译：存储器件和相应的制造方法防止掺杂剂从垂直NAND串的硅帽不期望地扩散到NAND串的沟道膜。最初，在交替的控制栅极层和电介质层的堆叠中提供存储器孔。记忆孔填充有环形膜和介质芯填料。将介质芯填料从存储孔的顶部回蚀到最顶层的控制栅层，形成空隙。在沉积形成硅帽的n +掺杂硅之前，在空隙中沉积掺杂剂阻挡层。掺杂剂阻挡衬垫可以是导电材料，例如掺杂有碳的金属或多晶硅。然后在硅帽的顶部上方形成导电通孔，并与硅帽的顶部对准。可以在导电通孔上形成位线。

44. 发明申请

US20160172045A1 Partial Block Erase For Open Block Reading In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的块读取部分块擦除
公开(公告)号：US20160172045A1
公开(公告)日：2016-06-16
申请号：US14794242
申请日：2015-07-08
申请人： SanDisk Technologies Inc.
发明人： Pitamber Shukla , Henry Chin , Dana Lee , Cynthia Hsu
IPC分类号： G11C16/16 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/16 , G11C11/5628 , G11C16/0483 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C2211/5644
摘要： A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.
摘要翻译：非易失性存储器系统通过在编程之前分析块的未编程区域来确定读取干扰的可能性来缓解开放块读取的影响。系统可以确定与存储块的开放块读取相关联的读取计数值和/或执行部分块擦除验证。为了减轻开放块读取干扰的影响，系统对存储器块的未编程区域执行部分块擦除和/或限制非编程区域中的编程。

45. 发明申请

US20160170682A1 TAG-BASED WEAR LEVELING FOR A DATA STORAGE DEVICE 有权
标题翻译：基于标签的数据存储设备的磨损水平
公开(公告)号：US20160170682A1
公开(公告)日：2016-06-16
申请号：US14572693
申请日：2014-12-16
申请人： SANDISK TECHNOLOGIES INC.
发明人： SWATI BAKSHI , NIAN NILES YANG , ALEXEI NABEREZHNOV , XINDE HU
IPC分类号： G06F3/06
CPC分类号： G06F3/0649 , G06F3/0616 , G06F3/0644 , G06F3/0647 , G06F3/0679 , G06F3/0688
摘要： A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.
摘要翻译：数据存储装置包括存储器。一种方法包括：基于第一区域与一组标签的第一标签相关联的确定，在损耗平衡过程期间，对存储器的一组区域的第一区域进行去分配。基于与该区域相关联的健康度量，将该组区域中的每个区域分配给该组标签的标签。健康度量基于误码率（BER），编程/擦除周期（PEC）计数，PEC条件度量或其组合。响应于选择第一区域，在磨损平整过程期间将信息从存储器的第一区域复制到第二区域。

46. 发明授权

US09368601B2 Method for forming oxide below control gate in vertical channel thin film transistor 有权
标题翻译：在垂直沟道薄膜晶体管中在控制栅极下方形成氧化物的方法
公开(公告)号：US09368601B2
公开(公告)日：2016-06-14
申请号：US14193451
申请日：2014-02-28
申请人： SanDisk 3D LLC
发明人： Michiaki Sano , Kensuke Yamaguchi , Akira Nakada , Naohito Yanagida
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L21/28 , H01L29/04 , H01L27/115
CPC分类号： H01L29/66666 , H01L21/28238 , H01L27/11556 , H01L27/11582 , H01L29/04 , H01L29/7827
摘要： A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
摘要翻译：垂直沟道晶体管的制造工艺提供所需的控制栅 - 漏重叠以及控制栅极与下面的金属线之间的充分隔离。晶体管的主体形成在诸如柱状的金属线上。金属线被氧化形成具有膨胀体积的金属氧化物区域。然后沉积栅极绝缘体材料和控制栅极材料。蚀刻所得到的结构以形成用于每个晶体管的单独的控制栅极，并暴露金属氧化物。执行另外的蚀刻以去除金属氧化物，在控制栅极下和周围形成空隙。绝缘填充空隙。示例性实施例是垂直位线存储器件，其中晶体管将垂直位线连接到水平位线。

47. 发明授权

US09368509B2 Three-dimensional memory structure having self-aligned drain regions and methods of making thereof 有权
标题翻译：具有自对准漏极区域的三维存储器结构及其制造方法
公开(公告)号：US09368509B2
公开(公告)日：2016-06-14
申请号：US14514925
申请日：2014-10-15
申请人： SanDisk Technologies, Inc.
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L21/336 , H01L29/76 , G11C11/34 , H01L27/115 , H01L29/51 , H01L29/417 , H01L21/223 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/2236 , H01L21/76802 , H01L21/76877 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/41741 , H01L29/511 , H01L29/518 , H01L29/7827
摘要： A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.
摘要翻译：可以通过交替的多个第一材料层和第二材料层的堆叠并通过具有与第一和第二材料层不同的组成的上覆临时材料层来形成存储器堆叠结构。存储器堆叠结构可以包括存储器膜和半导体沟道层。上覆的临时材料层被选择性地移除到堆叠以形成横向凹部。存储膜的一部分在横向凹槽周围被去除，并且掺杂剂被横向引入到半导体沟道的上部，以形成自对准的漏极区。

48. 发明授权

US09368207B2 Method of operating FET low current 3D re-ram 有权
标题翻译：操作FET低电流3D重新启动的方法
公开(公告)号：US09368207B2
公开(公告)日：2016-06-14
申请号：US14591546
申请日：2015-01-07
申请人： SanDisk 3D LLC
发明人： Abhijit Bandyopadhyay , Roy E Scheuerlein , Chandrasekhar R Gorla , Brian Le
IPC分类号： G11C13/00 , G11C11/56 , G11C7/00 , G11C16/34
CPC分类号： G11C13/0069 , G11C7/00 , G11C11/5614 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C16/3454 , G11C2013/0083 , G11C2213/71 , G11C2213/78 , G11C2213/79
摘要： Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.
摘要翻译：本文公开了操作ReRAM存储器。可以在最初对它们进行编程之前训练存储器单元。训练可能有助于建立渗透路径。在某些方面，当训练和编程时，晶体管限制存储器单元的电流。在训练期间使用更高的电流限制，这调节存储器单元以进行更好的编程。非存储器可以在单极模式下操作。存储器单元可以存储每个存储器单元的多个位。可以将存储器单元从其当前状态直接设置为一个至少两个数据状态。存储单元可以直接复位到具有下一个最高电阻的状态。诸如脉冲宽度和/或幅度的程序条件可以取决于存储器单元被设置到的状态。较高的能量可用于编程更高的电流状态。

49. 发明授权

US09367246B2 Performance optimization of data transfer for soft information generation 有权
标题翻译：软信息生成的数据传输性能优化
公开(公告)号：US09367246B2
公开(公告)日：2016-06-14
申请号：US13963444
申请日：2013-08-09
申请人： SanDisk Enterprise IP LLC
发明人： Jack Edward Frayer , Aaron K. Olbrich
IPC分类号： G06F3/00 , G06F3/06 , G06F11/10 , H03M13/37 , H03M13/45
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/068 , G06F11/1048 , H03M13/3723 , H03M13/3769 , H03M13/45
摘要： A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values.
摘要翻译：单个命令从存储器的相同部分启动一个或多个附加读取操作的第一读取操作和序列。在第一读取操作提供使得可用于请求设备和/或模块的第一多个数据值之后，一个或多个附加读取操作可终止。在一些实现中，第一多个数据值包括硬信息值。后续的多个数据值从存储器的相同部分生成直到发生终止事件。在一些实现中，直到发生终止事件，通过将最新读取的多个数据值与先前产生的混合多个数据值和第一多个数据值中的一个组合来生成相应的混合多个数据值。每个混合多个数据值表示相应的多个软信息值。

50. 发明申请

US20160163397A1 INTRINSIC MEMORY BLOCK HEALTH MONITORING 有权
标题翻译：内在记忆体健康监测
公开(公告)号：US20160163397A1
公开(公告)日：2016-06-09
申请号：US14560698
申请日：2014-12-04
申请人： SanDisk Technologies Inc.
发明人： Rohit Sehgal , Nian Niles Yang
IPC分类号： G11C16/34 , G11C16/26 , G11C16/10
CPC分类号： G11C16/349 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C29/4401 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： A memory system or flash card may monitor the health of memory and the user data stored by detecting and storing a number of bits in error for each block. This detection can be used to determine where user data should be programmed and which blocks should be cycled. The erratic bits are detected after a programming and the listing for each block is updated. When the erratic bits exceed a threshold for a particular block, that block may be cycled or retired.
摘要翻译：存储器系统或闪存卡可以通过检测和存储每个块的错误位数来监视存储器的健康状况和存储的用户数据。该检测可用于确定用户数据应被编程的位置以及应循环的块。在编程之后检测到不稳定的位，并且更新每个块的列表。当不规则位超过特定块的阈值时，该块可以循环或退出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式