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1. 发明授权

US09939831B2 Fast settling low dropout voltage regulator 有权
公开(公告)号：US09939831B2
公开(公告)日：2018-04-10
申请号：US14992376
申请日：2016-01-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Saurabh Verma , Subodh Taigor , Sridhar Yadala
IPC分类号： G05F1/00 , G05F1/575
CPC分类号： G05F1/575
摘要： Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a controller and then is ended when the output voltage of the voltage regulator is within a first voltage of the desired regulation voltage or has overshot the desired regulation voltage by a second voltage (e.g., has overshot the desired regulation voltage by 150 mV).

2. 发明申请

US20160352217A1 Dynamic Clock Period Modulation Scheme for Variable Charge Pump Load Currents 有权
标题翻译：可变电荷泵负载电流的动态时钟周期调制方案
公开(公告)号：US20160352217A1
公开(公告)日：2016-12-01
申请号：US14724067
申请日：2015-05-28
申请人： SanDisk Technologies Inc.
发明人： Gooty Sukumar Reddy , Potnuru Venkata Pradeep Kumar , Sridhar Yadala
IPC分类号： H02M3/07 , H03K3/354
CPC分类号： H02M3/07 , H02M1/08 , H02M1/44 , H02M3/00 , H02M2001/0003 , H03K3/0231 , H03K3/354 , H03K17/687 , H03L7/18
摘要： A charge pump is connected to receive a supply voltage and a clock signal and generate an output voltage. The charge pump is connected to the supply voltage through a transistor whose gate voltage is set by a regulation voltage determined by feedback from the output voltage. The current supplied to the charge pump through this transistor is mirrored in a section that generates the dock signal, where the mirrored current is used by a current controller oscillator. This allows the pump's clock frequency to linearly track the load current, improving the pump's efficiency.
摘要翻译：电荷泵被连接以接收电源电压和时钟信号并产生输出电压。电荷泵通过晶体管连接到电源电压，晶体管的栅极电压由通过输出电压的反馈确定的调节电压设置。通过该晶体管提供给电荷泵的电流反映在产生停靠信号的部分中，其中镜像电流由电流控制器振荡器使用。这允许泵的时钟频率线性跟踪负载电流，提高泵的效率。

3. 发明授权

US08981750B1 Active regulator wake-up time improvement by capacitive regulation 有权
标题翻译：通过电容调节来调节主动调节器唤醒时间
公开(公告)号：US08981750B1
公开(公告)日：2015-03-17
申请号：US13972100
申请日：2013-08-21
申请人： SanDisk Technologies Inc.
发明人： Deepak Kumar Meher , Sridhar Yadala , Subodh Taigor
IPC分类号： G05F1/40 , H02M3/156
CPC分类号： H02M3/156 , G05F1/56 , G05F1/575 , G11C5/148
摘要： An active voltage regulator circuit having improved wake-up response is presented. The circuit includes an op-amp whose output is connected to a pass device for supplying the output level, and has both capacitive and resistive parts in its feedback loop. When the regulator is enabled, the capacitive elements are initially connected, followed after a delay by the resistive elements of the feedback loop.
摘要翻译：提出了一种具有改善的唤醒响应的有源稳压电路。该电路包括一个运算放大器，其输出端连接到用于提供输出电平的通过装置，并且在其反馈回路中具有电容和电阻部分。当调节器被使能时，电容元件最初被连接，然后在反馈回路的电阻元件延迟之后。

4. 发明申请

US20170256955A1 Efficient Peak Current Management In A Multi-Die Stack 审中-公开
公开(公告)号：US20170256955A1
公开(公告)日：2017-09-07
申请号：US15099496
申请日：2016-04-14
申请人： SanDisk Technologies Inc.
发明人： Sravanti Addepalli , Sridhar Yadala
IPC分类号： H02J4/00 , H04L12/40
CPC分类号： G11C16/30 , G11C5/14 , H04L12/40045
摘要： Techniques for managing the distribution of power among competing electronic devices such as semiconductor die are presented. Each device may be connected to a common power supply and sources a current on a load bus based on an estimated current consumption of a next desired state. However, before doing this, the device performs an internal check to determine whether there is a sufficient available current. The device decreases a logical value of the system current specification by the increase in current which is desired. A resulting voltage (Vspec) is compared to a voltage of the load bus (Vcontact). If Vcontact

5. 发明申请

US20170199536A1 FAST SETTLING LOW DROPOUT VOLTAGE REGULATOR 有权
公开(公告)号：US20170199536A1
公开(公告)日：2017-07-13
申请号：US14992376
申请日：2016-01-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Saurabh Verma , Subodh Taigor , Sridhar Yadala
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a controller and then is ended when the output voltage of the voltage regulator is within a first voltage of the desired regulation voltage or has overshot the desired regulation voltage by a second voltage (e.g., has overshot the desired regulation voltage by 150 mV).

6. 发明授权

US09563213B2 On chip ZQ calibration resistor trimming 有权
标题翻译：片上ZQ校准电阻修剪
公开(公告)号：US09563213B2
公开(公告)日：2017-02-07
申请号：US14966891
申请日：2015-12-11
申请人： SanDisk Technologies Inc.
发明人： Sravanti Addepalli , Sridhar Yadala
IPC分类号： H03K19/003 , H03K17/16 , G05F1/46 , G11C16/06 , H03K19/00
CPC分类号： G05F1/463 , G11C5/147 , G11C7/04 , G11C16/06 , G11C2207/2254 , H03K19/0005
摘要： Techniques for trimming an on chip ZQ calibration resistor are disclosed. The on chip ZQ calibration resistor alleviates the need for an external ZQ calibration resistor. The on chip ZQ calibration resistor allows for a faster ZQ calibration. The trimming of on chip ZQ calibration resistor may be used to account for process variation. A correction mechanism may be used to account for temperature variation. Some of the circuitry that is used for ZQ calibration is also used for trimming the on-chip calibration resistor. This circuitry may include operational amplifiers, current mirrors, transistors, etc. The dual use of the circuitry can eliminate offset errors in an operational amplifier. The dual use can eliminate current mirror mismatch. Therefore, the trimming accuracy may be improved. The dual use also reduces the amount of circuitry that is needed for trimming the on chip ZQ calibration resistor. Thus, transistor count and chip size is reduced.
摘要翻译：公开了用于修整片上ZQ校准电阻器的技术。片上ZQ校准电阻缓解了对外部ZQ校准电阻的需求。片上ZQ校准电阻允许更快的ZQ校准。片上ZQ校准电阻的修整可用于考虑工艺变化。可以使用校正机制来解释温度变化。用于ZQ校准的一些电路也用于微调片上校准电阻。该电路可以包括运算放大器，电流镜，晶体管等。电路的双重用途可以消除运算放大器中的偏移误差。双重用途可以消除电流镜的不匹配。因此，可以提高修整精度。双重用途还减少了修整片上ZQ校准电阻所需的电路数量。因此，晶体管数量和芯片尺寸减小。

7. 发明授权

US09531382B1 Search for impedance calibration 有权
标题翻译：搜索阻抗校准
公开(公告)号：US09531382B1
公开(公告)日：2016-12-27
申请号：US14842032
申请日：2015-09-01
申请人： SanDisk Technologies Inc.
发明人： Hitoshi Miwa , Sravanti Addepalli , Sridhar Yadala
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/0005 , H03K19/003
摘要： A non-volatile storage system includes an impedance code calibration circuit. The device has a first variable impedance circuit and a second variable impedance circuit coupled to a calibration node. The device has a control circuit configured to access a previous impedance code for a previous impedance calibration and to divide the previous impedance code into a main impedance code and a remainder impedance code. The control circuit is configured to perform a search for a new impedance code starting with the main impedance code applied to the first variable impedance circuit while maintaining the remainder impedance code to the second variable impedance circuit. The control circuit is configured to add the final impedance code for the first variable impedance circuit with the remainder impedance code to produce a new impedance code for the impedance calibration.
摘要翻译：非易失性存储系统包括阻抗代码校准电路。该装置具有耦合到校准节点的第一可变阻抗电路和第二可变阻抗电路。该装置具有控制电路，该控制电路被配置为访问先前阻抗校准的先前阻抗代码，并将先前的阻抗代码分成主阻抗代码和余数阻抗代码。控制电路被配置为执行从施加到第一可变阻抗电路的主阻抗代码开始的新阻抗代码，同时将剩余阻抗代码保持到第二可变阻抗电路。控制电路被配置为将第一可变阻抗电路的最终阻抗代码与剩余阻抗代码相加以产生用于阻抗校准的新阻抗代码。

8. 发明申请

US20160182044A1 On Chip ZQ Calibration Resistor Trimming 有权
标题翻译：片上ZQ校准电阻修剪
公开(公告)号：US20160182044A1
公开(公告)日：2016-06-23
申请号：US14966891
申请日：2015-12-11
申请人： SanDisk Technologies Inc.
发明人： Sravanti Addepalli , Sridhar Yadala
IPC分类号： H03K19/00 , G11C16/06
CPC分类号： G05F1/463 , G11C5/147 , G11C7/04 , G11C16/06 , G11C2207/2254 , H03K19/0005
摘要： Techniques for trimming an on chip ZQ calibration resistor are disclosed. The on chip ZQ calibration resistor alleviates the need for an external ZQ calibration resistor. The on chip ZQ calibration resistor allows for a faster ZQ calibration. The trimming of on chip ZQ calibration resistor may be used to account for process variation. A correction mechanism may be used to account for temperature variation. Some of the circuitry that is used for ZQ calibration is also used for trimming the on-chip calibration resistor. This circuitry may include operational amplifiers, current mirrors, transistors, etc. The dual use of the circuitry can eliminate offset errors in an operational amplifier. The dual use can eliminate current mirror mismatch. Therefore, the trimming accuracy may be improved. The dual use also reduces the amount of circuitry that is needed for trimming the on chip ZQ calibration resistor. Thus, transistor count and chip size is reduced.
摘要翻译：公开了用于修整片上ZQ校准电阻器的技术。片上ZQ校准电阻缓解了对外部ZQ校准电阻的需求。片上ZQ校准电阻允许更快的ZQ校准。片上ZQ校准电阻的修整可用于考虑工艺变化。可以使用校正机制来解释温度变化。用于ZQ校准的一些电路也用于微调片上校准电阻。该电路可以包括运算放大器，电流镜，晶体管等。电路的双重用途可以消除运算放大器中的偏移误差。双重用途可以消除电流镜的不匹配。因此，可以提高修整精度。双重用途还减少了修整片上ZQ校准电阻所需的电路数量。因此，晶体管数量和芯片尺寸减小。

9. 发明授权

US09704591B2 Temperature independent reference current generation for calibration 有权
公开(公告)号：US09704591B2
公开(公告)日：2017-07-11
申请号：US15082241
申请日：2016-03-28
申请人： SanDisk Technologies Inc.
发明人： Subodh Prakash Taigor , Sridhar Yadala , Rangarao Samineni
IPC分类号： G05F3/16 , G11C16/28 , G05F1/46 , G11C16/06 , H03K19/00 , G11C5/14 , G11C7/04
CPC分类号： G11C16/28 , G05F1/463 , G05F3/16 , G11C5/147 , G11C7/04 , G11C16/06 , G11C2207/2254 , H03K19/0005
摘要： Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be based on a reference voltage and a target calibration resistance.

10. 发明申请

US20160380532A1 CLOCK FREEZING TECHNIQUE FOR CHARGE PUMPS 审中-公开
标题翻译：充电泵的时钟冷冻技术
公开(公告)号：US20160380532A1
公开(公告)日：2016-12-29
申请号：US14752007
申请日：2015-06-26
申请人： SANDISK TECHNOLOGIES INC.
发明人： Gooty Sukumar Reddy , Sridhar Yadala , Saurabh Verma
IPC分类号： H02M3/07 , G11C16/30
CPC分类号： H02M3/07 , G11C5/145 , G11C7/22 , G11C11/5621 , G11C16/30 , G11C16/32
摘要： Methods and systems for generating voltages greater than a supply voltage are described. A charge pump system may generate a boosted output voltage greater than the supply voltage using one or more charge pump stages that are arranged in series between the supply voltage and the boosted output voltage. The charge pump system may include clock freezing circuitry that eliminates glitches in clock signals used for driving the one or more charge pump stages. In one example, the clock freezing circuitry may freeze a clock signal that drives a charge pump stage (i.e., prevent the clock signal from switching) when a feedback flag of the charge pump system is in a disable state (e.g., is low). When the feedback flag is in an enable state (e.g., is high), then the clock signal may toggle between a high state and a low state.
摘要翻译：描述用于产生大于电源电压的电压的方法和系统。电荷泵系统可以使用在电源电压和升压的输出电压之间串联布置的一个或多个电荷泵级来产生大于电源电压的升压输出电压。电荷泵系统可以包括时钟冻结电路，其消除用于驱动一个或多个电荷泵级的时钟信号的毛刺。在一个示例中，当电荷泵系统的反馈标志处于禁用状态（例如，低）时，时钟冻结电路可以冻结驱动电荷泵级的时钟信号（即，防止时钟信号切换）。当反馈标志处于使能状态（例如，高电平）时，时钟信号可以在高状态和低电平状态之间切换。

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