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41. 发明申请

US20130320495A1 Integration of Non-Noble DRAM Electrode 有权
标题翻译：非贵重DRAM电极的集成
公开(公告)号：US20130320495A1
公开(公告)日：2013-12-05
申请号：US13738510
申请日：2013-01-10
申请人： INTERMOLECULAR, INC.
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Edward L. Haywood , Hiroyuki Ode , Gerald Richardson
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01L28/75 , H01L28/92
摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
摘要翻译：描述形成电容器堆叠的方法。在本发明的一些实施例中，第一电极结构由多种材料构成。在基板上方形成第一材料。蚀刻第一材料的一部分。在第一材料上方形成第二材料。蚀刻第二材料的一部分。可选地，第一电极结构接受退火处理。介电材料形成在第一电极结构之上。可选地，电介质材料接受退火处理。在电介质材料上方形成第二电极材料。通常，电容器堆叠接收退火处理。

42. 发明申请

US20130234291A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130234291A1
公开(公告)日：2013-09-12
申请号：US13733723
申请日：2013-01-03
申请人： Noboru MIYAMOTO , Yoshikazu TSUNODA
发明人： Noboru MIYAMOTO , Yoshikazu TSUNODA
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01G4/232 , H01G4/30 , H01G4/33 , H01G4/40 , H01L23/49562 , H01L23/49589 , H01L23/642 , H01L24/32 , H01L25/16 , H01L28/82 , H01L28/86 , H01L28/90 , H01L2924/13055 , H01L2924/00
摘要： A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions.
摘要翻译：半导体器件包括电连接到半导体元件的上表面的第一电极，与半导体元件的下表面电连接并具有多个第一梳状指部的第一内部电极和连接多个电连接到第一内部电极的第二电极，与第一电极的下表面电连接并具有多个第二梳形指状部分的第二内部电极和连接多个第二梳状部分的第二连接部分，梳状指部分在一起，多个第二梳状指部分与多个第一梳状指部分相互交错但不接触;以及下部电介质，其填充多个第一梳状指部分与多个第二梳状指状部分之间的空间部分。

43. 发明申请

US20130221483A1 Trench Capacitors and Methods of Forming the Same 有权
公开(公告)号：US20130221483A1
公开(公告)日：2013-08-29
申请号：US13405092
申请日：2012-02-24
申请人： Thomas Popp , Stefan Pompl , Rudolf Berger
发明人： Thomas Popp , Stefan Pompl , Rudolf Berger
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L27/0805
摘要： A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

44. 发明申请

US20130200482A1 SHALLOW TRENCH ISOLATION FOR DEVICE INCLUDING DEEP TRENCH CAPACITORS 失效
标题翻译：用于包括深层电容电容器的器件的低温隔离
公开(公告)号：US20130200482A1
公开(公告)日：2013-08-08
申请号：US13366576
申请日：2012-02-06
申请人： Sunfei FANG , Oleg GLUSCHENKOV , Byeong Y. KIM , Rishikesh KRISHNAN , Daewon YANG
发明人： Sunfei FANG , Oleg GLUSCHENKOV , Byeong Y. KIM , Rishikesh KRISHNAN , Daewon YANG
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10861 , H01L21/76224 , H01L29/66181 , H01L29/945
摘要： A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
摘要翻译：在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

45. 发明授权

US08502341B2 Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device 有权
标题翻译：沟槽型电容器，具有该沟槽型电容器的半导体器件和具有半导体器件的半导体模块
公开(公告)号：US08502341B2
公开(公告)日：2013-08-06
申请号：US13021333
申请日：2011-02-04
申请人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

46. 发明申请

US20130168812A1 MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有稳定运动的记忆体电容器及其制造方法
公开(公告)号：US20130168812A1
公开(公告)日：2013-07-04
申请号：US13426848
申请日：2012-03-22
申请人： TZUNG-HAN LEE , CHUNG-LIN HUANG , RON-FU CHU
发明人： TZUNG-HAN LEE , CHUNG-LIN HUANG , RON-FU CHU
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L27/10852
摘要： A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.
摘要翻译：一种具有坚固的护城河的存储电容器的制造方法，包括以下步骤：提供衬底; 在具有护城河的基板上形成图案化的牺牲层以分离单元区域和周边区域; 在所述牺牲层上形成支撑层并填充所述护城河以形成环形构件，其中所述支撑层和所述牺牲层排列成对准以形成堆叠结构; 在所述基板上形成多排电容器沟槽，其中所述电容器沟槽在所述堆叠结构中间隔地形成; 以及在所述支撑层上形成导电层，并覆盖所述基板和限定所述电容器沟槽的所述堆叠结构的内表面。

47. 发明申请

US20130148404A1 ANTIFUSE-BASED MEMORY CELLS HAVING MULTIPLE MEMORY STATES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有多个记忆状态的基于抗病毒剂的记忆细胞及其形成方法
公开(公告)号：US20130148404A1
公开(公告)日：2013-06-13
申请号：US13314580
申请日：2011-12-08
申请人： Abhijit Bandyopadhyay , Roy E. Scheuerlein , Peter Rabkin
发明人： Abhijit Bandyopadhyay , Roy E. Scheuerlein , Peter Rabkin
IPC分类号： G11C17/00 , H01L29/92
CPC分类号： H01L28/40 , G11C11/5692 , G11C17/165 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/10 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.
摘要翻译：在一些方面，提供了一种存储单元，其包括转向元件和与转向元件串联耦合的金属 - 绝缘体金属（“MIM”）堆叠。 MIM堆叠包括第一介电材料层和设置在第一介电材料层上的第二电介质材料层，而没有金属或其它导电层设置在第一介电材料层和第二电介质材料层之间。提供了许多其他方面。

48. 发明申请

US20130130465A1 METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS 审中-公开
标题翻译：形成具有包含结晶区域的复合介电层的集成电路电容器的方法
公开(公告)号：US20130130465A1
公开(公告)日：2013-05-23
申请号：US13716901
申请日：2012-12-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoo Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoo Oh
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

49. 发明申请

US20130127013A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130127013A1
公开(公告)日：2013-05-23
申请号：US13679445
申请日：2012-11-16
申请人： SK hynix Inc.
发明人： Cheol Hwan PARK , Dong Sauk KIM
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/91
摘要： In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact.
摘要翻译：在半导体装置中，在存储节点之间形成支撑壁，以更有效地防止电容器的倾斜，并且使用镶嵌工艺形成存储节点，这可以增加每个存储节点与存储节点接触之间的接触面积。

50. 发明申请

US20130127012A1 Semiconductor Devices and Methods of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130127012A1
公开(公告)日：2013-05-23
申请号：US13603478
申请日：2012-09-05
申请人： Tae-woong Koo
发明人： Tae-woong Koo
IPC分类号： H01L29/92 , H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/91
摘要： A method of manufacturing a semiconductor device including forming on a substrate an insulating interlayer through which a capacitor contact is interposed; forming on the insulating interlayer a first upper electrode having an opening through which the capacitor contact is exposed; forming a first dielectric layer pattern on a lateral wall of the opening; forming a lower electrode on the first dielectric layer pattern formed in the opening and the capacitor contact; forming a second dielectric layer pattern on the lower electrode formed in the opening and the first dielectric layer pattern; and forming on the second dielectric layer pattern a second upper electrode so as to fill the opening and to contact the first upper electrode. The semiconductor device may prevent a lower electrode of a capacitor from collapsing.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成插入电容器接触的绝缘中间层; 在所述绝缘中间层上形成具有开口的第一上电极，所述电容器触点暴露在所述开口中; 在所述开口的侧壁上形成第一电介质层图案; 在形成在开口中的第一介电层图案和电容器触点上形成下电极; 在形成在开口中的下电极和第一介电层图案上形成第二电介质层图案; 以及在所述第二电介质层图案上形成第二上电极，以填充所述开口并接触所述第一上电极。半导体器件可以防止电容器的下电极折叠。

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