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41. 发明授权

US07396727B2 Transistor of semiconductor device and method for fabricating the same 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US07396727B2
公开(公告)日：2008-07-08
申请号：US11615812
申请日：2006-12-22
申请人： Jeong-Ho Park
发明人： Jeong-Ho Park
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/105 , H01L29/7827
摘要： A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel region having a cylindrical shape over the source region; a drain region formed over the channel region; a gate insulation layer formed over the source region, a side of the channel region, and the drain region; and a gate conductor extending over an upper portion and one side of the channel region.
摘要翻译：可以用垂直晶体管结构有效地控制短沟道效应的晶体管。这种结构可以防止由热载流子效应引起的晶体管性能的劣化。晶体管具有在半导体衬底上具有注入的杂质离子浓度的源区; 在所述源极区域上具有圆柱形状的沟道区域; 漏极区，形成在所述沟道区上; 形成在源极区域，沟道区域侧和漏极区域上的栅极绝缘层; 以及在沟道区域的上部和一侧延伸的栅极导体。

42. 发明申请

US20080124873A1 Method of fabricating semiconductor device having gate dielectrics with different thicknesses 有权
公开(公告)号：US20080124873A1
公开(公告)日：2008-05-29
申请号：US11826714
申请日：2007-07-18
申请人： Sun-hak Lee , Kwang-dong Yoo , Sang-bae Yi , Soo-cheol Lee , Mueng-ryul Lee
发明人： Sun-hak Lee , Kwang-dong Yoo , Sang-bae Yi , Soo-cheol Lee , Mueng-ryul Lee
IPC分类号： H01L21/8236
CPC分类号： H01L21/823857 , H01L21/82385 , H01L21/823892
摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

43. 发明授权

US07238579B2 Semiconductor device for reducing photovolatic current 失效
标题翻译：用于降低光伏电流的半导体器件
公开(公告)号：US07238579B2
公开(公告)日：2007-07-03
申请号：US11003279
申请日：2004-12-03
申请人： Bradley P. Smith , Edward O. Travis
发明人： Bradley P. Smith , Edward O. Travis
IPC分类号： H01L21/8236
CPC分类号： H01L23/552 , H01L2924/0002 , Y02P80/30 , H01L2924/00
摘要： A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.
摘要翻译：在P和N阱之间具有共同边界的半导体器件易于被认为主要由撞击该共同边界的光子产生的光电流。据认为，在边界PN结处产生的电子/空穴对被分离出来。如果与井的这些金属连接的面积相对于边界的长度小，则光电流可以具有足够的电流密度来破坏与阱的金属连接。通过充分覆盖公共边界以减少击中共同边界的光子的数量，该光电流可以降低到破坏性水平以下。连接的表面积也可以增加以减轻问题。

44. 发明授权

US07217606B2 Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures 有权
标题翻译：在（110），（111），（311），（511）和大块，薄膜结构的高阶表面上形成垂直亚微米CMOS晶体管的方法
公开(公告)号：US07217606B2
公开(公告)日：2007-05-15
申请号：US10222997
申请日：2002-08-19
申请人： Leonard Forbes , Wendell P. Noble , Alan R. Reinberg
发明人： Leonard Forbes , Wendell P. Noble , Alan R. Reinberg
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336 , H01L21/8236
CPC分类号： H01L29/78648 , H01L21/823807 , H01L21/823885 , H01L27/1203 , H01L29/045 , H01L29/78639 , H01L29/78642
摘要： A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.
摘要翻译：一种用于形成NMOS和PMOS晶体管的方法，其包括沿着较高阶取向切割衬底并在其垂直表面上制造深亚微米级的NMOS和PMOS晶体管。互补的NMOS和PMOS晶体管形成CMOS晶体管对。晶体管优选地用于诸如存储器电路（例如DRAM）的结构中，这些DRAM又在基于处理器的系统中使用。理想地，深亚微米NMOS和PMOS晶体管以速度饱和运行，以实现最佳切换操作。

45. 发明申请

US20070072334A1 Semiconductor fabrication process employing spacer defined vias 审中-公开
标题翻译：半导体制造工艺采用间隔件定义的通孔
公开(公告)号：US20070072334A1
公开(公告)日：2007-03-29
申请号：US11239282
申请日：2005-09-29
申请人： Marius Orlowski , Kathleen Yu
发明人： Marius Orlowski , Kathleen Yu
IPC分类号： H01L21/00 , H01L21/8236
CPC分类号： H01L21/76835 , H01L21/76808 , H01L21/76811
摘要： A semiconductor fabrication process includes forming a first etch mask (131) that defines a first opening (132) and a second etch mask (140) that defines a second opening (142) overlying an interlevel dielectric (ILD) (108). The ILD (108) is etched to form a first via (154) defined by the first opening (132) and a second via (152) defined by the second opening (142). The first etch mask (131) may include a patterned hard mask layer (122) and the second etch mask may be a patterned photoresist layer (140). The first etch mask may further include spacers (130) adjacent sidewalls of the patterned hard mask layer (122). The patterned hard mask layer (122) may be a titanium nitride and the spacers (130) may be silicon nitride. The ILD (108) may be an CVD low-k dielectric layer overlying a CVD low-k etch stop layer (ESL) (106).
摘要翻译：半导体制造工艺包括形成限定第一开口（132）的第一蚀刻掩模（131）和限定覆盖层间电介质（IL））的第二开口（142）的第二蚀刻掩模（140）。蚀刻ILD（108）以形成由第一开口（132）限定的第一通孔（154）和由第二开口（142）限定的第二通孔（152）。第一蚀刻掩模（131）可以包括图案化的硬掩模层（122），并且第二蚀刻掩模可以是图案化的光致抗蚀剂层（140）。第一蚀刻掩模还可以包括与图案化的硬掩模层（122）的侧壁相邻的间隔物（130）。图案化的硬掩模层（122）可以是氮化钛，并且间隔物（130）可以是氮化硅。 ILD（108）可以是覆盖CVD低k蚀刻停止层（ESL）（106）的CVD低k电介质层。

46. 发明授权

US07186619B2 Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET 有权
标题翻译：集成了负差分电阻（NDR）FET的绝缘栅场效应晶体管
公开(公告)号：US07186619B2
公开(公告)日：2007-03-06
申请号：US10867006
申请日：2004-06-14
申请人： Tsu-Jae King
发明人： Tsu-Jae King
IPC分类号： H01L21/8236
CPC分类号： G11C5/142 , B82Y10/00 , G11C11/39 , H01L21/28273 , H01L21/28282 , H01L27/088 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： A semiconductor device is disclosed that includes integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.
摘要翻译：公开了一种半导体器件，其包括集成绝缘栅场效应晶体管（IGFET）元件和一个或多个负差分电阻（NDR）场效应晶体管元件，其组合并形成在公共基板上。因此，包括逻辑和存储器在内的各种电路通过常规和具有NDR功能的FET的组合来实现。因为这两种类型的元件共享许多共同特征，所以它们可以用通常的加工操作来制造，以便在制造设备中实现更好的集成。

47. 发明授权

US06998316B2 Method for fabricating read only memory including a first and second exposures to a photoresist layer 有权
标题翻译：一种用于制造只读存储器的方法，包括对光致抗蚀剂层的第一和第二曝光
公开(公告)号：US06998316B2
公开(公告)日：2006-02-14
申请号：US10708228
申请日：2004-02-18
申请人： Tahorng Yang , Henry Chung , Cheng-Chen Calvin Hsueh , Ching-Yu Chang
发明人： Tahorng Yang , Henry Chung , Cheng-Chen Calvin Hsueh , Ching-Yu Chang
IPC分类号： H01L21/8236 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L27/1126 , H01L27/105 , H01L27/11293 , Y10S438/949
摘要： A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.
摘要翻译：只读存储器的制造方法提供具有存储单元区域和外围电路区域的衬底。存储单元区域具有存储单元阵列，并且外围电路区域具有晶体管。在存储单元区域中形成具有多个第一开口的精确层。第一开口在存储单元阵列中的每个存储单元的沟道区之上，并且第一开口的临界尺寸相同。在基板上形成具有第二开口和第三开口的掩模层。第二开口位于预编码存储单元区域上，并且第三开口位于晶体管栅极之上。执行离子注入以对预编码存储单元区域中的存储单元进行编码，并使用精确层和掩模层作为掩模来调节晶体管的阈值电压。

48. 发明授权

US06969642B2 Method of controlling implantation dosages during coding of read-only memory devices 有权
公开(公告)号：US06969642B2
公开(公告)日：2005-11-29
申请号：US10627026
申请日：2003-07-25
申请人： Ta Hung Yang , Tien Chu Yang , Tsung Hsien Wu , Chunghsien Lee , Kuo Chuang Hui
发明人： Ta Hung Yang , Tien Chu Yang , Tsung Hsien Wu , Chunghsien Lee , Kuo Chuang Hui
IPC分类号： G11C16/10 , H01L21/82 , H01L21/8236 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115
CPC分类号： H01L27/1126 , H01L27/112
摘要： A method of controlling implantation dosages during coding of read-only memory (ROM) devices is disclosed. According to the method, a semi-manufactured ROM device having a plurality of gates with identically designed gate widths is formed, followed by the formation of a first photoresist layer over the semi-manufactured ROM device. The first photoresist layer is selectively exposed to develop a pattern of pre-code openings, with each pre-code opening being positioned over a word line and between two adjacent bit lines intersecting the word line and with the pre-code openings having substantially identical sizes. A second photoresist layer is then formed over the first photoresist layer, followed by selectively exposing the second photoresist layer to develop a pattern of real-code openings therein, with the real-code openings having substantially identical sizes. A tuned dosage of ions is then implanted through intersections of the real-code and pre-code openings to thereby code the ROM device.

49. 发明授权

US06964904B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06964904B2
公开(公告)日：2005-11-15
申请号：US10734227
申请日：2003-12-15
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/76 , H01L21/8236 , H01L23/52 , H01L29/423 , H01L29/49 , H01L29/76 , H01L29/78
CPC分类号： H01L21/28123 , H01L21/28061 , H01L21/28247 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses method for manufacturing semiconductor device employing an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film is formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film using the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.
摘要翻译：本发明公开了采用EXTIGATE结构制造半导体器件的方法。根据该方法，对器件隔离膜的预定厚度进行蚀刻以形成凹陷。然后用第二氮化物膜填充凹部。在整个表面上形成第二氮化物膜和多晶硅膜上的阻挡金属膜，金属层和第三氮化物膜的堆叠结构，并通过光刻工艺蚀刻以形成栅电极。绝缘膜间隔物沉积在栅电极的侧壁上。使用第三氮化物膜图案和绝缘膜间隔物作为掩模的多晶硅膜的暴露部分在多晶硅膜图案的侧壁上形成多晶硅膜图案和氧化物膜。

50. 发明授权

US06960510B2 Method of making sub-lithographic features 失效
标题翻译：制作亚光刻特征的方法
公开(公告)号：US06960510B2
公开(公告)日：2005-11-01
申请号：US10187579
申请日：2002-07-01
申请人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
发明人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L21/033 , H01L21/265 , H01L21/28 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L21/26586 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L21/31144
摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.
摘要翻译：提供了形成具有亚光刻尺寸的结构的方法。该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

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